Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.
Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.
Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.
Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.
Change-Id: Icfe917f788814c329659c44e298cf05d6e3d0dd9
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Update preloaded_bl33_base for legacy product for Yocto.
The Yocto Jenkins build was initially configured to build products
where the starting of the DDR is from 0x0000 0000. And if there is
no NS_image_offset set, the Jenkins is not able to acquire the correct
address offset to boot up the system. However, in the direct OS boot,
there is no issue as the user shall always include the address offset
during the compilation phase. Otherwise, the code shall execute the
default address offset. Besides that, this also provides the
flexibility to user to customize their SoC design by not restricted
to the default address.
SDMMC block size. It was changed due to the need when boot to Linux.
Kernel.itb size is big thus we have to increase the available reading
block size. Otherwise for normal U-boot and Zephyr it shall not be
reading a big block size to avoid "garbage" data.
Change-Id: I1c2a22db28bf0ada734563e40efd4f5749951273
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.
Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Due to design issue, updated system counter back to hardcoded 400MHz
Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Add QSPI ECC new opcodes for Linux to access to SDM register
Change-Id: I548e30340320ae2c2c9d60d20b218ee844516d64
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2 image has exceeded its limits.
Change-Id: I7542f5ea001542450695d48e8126bcca8728d76a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
This patch is to restructure watchdog.
Move platform dependent MACROs to individual platform socfpga_plat_def.
Common watchdog code file and header file will remain for those common
declaration.
Change-Id: Ibb640f08ac313bbad6d9295596cb8ff26e3e626d
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This patch is used to enable platform enablement for
Agilex5 SoC FPGA.
New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU
3. Added ATF->Linux boot option
4. Added SMP support
5. Added HPS bridges support
6. Added EMULATOR support
7. Added DDR support
8. Added GICv3 Redistirbution init
9. Added SDMMC/NAND/Combo Phy support
10. Updated GIC as secure access
11. Added CCU driver support
12. Updated product name -> Agilex5
13. Updated register address based on y22ww52.2 RTL
14. Updated system counter freq to 400MHz
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb
Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibfaa47fb7a25176eebf06f4828bf9729d56f12ed
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The implementation shall apply to only Agilex and S10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422
This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properly the bridges
in SMC call or during reset.
The reset is also maskable as the SMC from uboot can
pass in the bridge mask when requesting for bridge
enable or disable.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie144518c591664ef880016c9b3706968411bbf21
Refactor NOC header to be shareable across both Stratix 10 and Agilex
platforms. This patch also removes redundant NOC declarations in system
manager header file.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6348b67a8b54c2ad19327d6b8c25ae37d25e4b4a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Define FPGA_CONFIG_SIZE and FPGA_CONFIG_ADDR in
platform-specific header. This is due to different
allocated sizes between platforms.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iac4fbf4d4940cdf31834a9d4332f9292870dee76
Platform handoff structure no longer includes boot source selection.
Hence, those settings can now be configured through socfpga_plat_def.h.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If7ec6a03bb25156a6670ebf8f77105c370b553f6
Refactored system manager driver to be shared across both intel platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d
Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through macros.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
