mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
fix(intel): update system counter back to 400MHz
Due to design issue, updated system counter back to hardcoded 400MHz Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang
parent
d0e400b3c6
commit
a72f86ac42
3 changed files with 64 additions and 61 deletions
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@ -9,14 +9,15 @@
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#define PLAT_SOCFPGA_DEF_H
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#include "agilex_system_manager.h"
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#include <lib/utils_def.h>
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#include <platform_def.h>
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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@ -64,17 +65,17 @@
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#define DEVICE4_BASE (0x2000000000)
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#define DEVICE4_SIZE (0x0100000000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe2b000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe2b000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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/*******************************************************************************
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* WDT related constants
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@ -84,19 +85,19 @@
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/*******************************************************************************
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* GIC related constants
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******************************************************************************/
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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/*******************************************************************************
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* SDMMC related pointer function
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******************************************************************************/
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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/*******************************************************************************
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* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
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@ -105,6 +106,6 @@
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#define L2_RESET_DONE_REG 0xFFD12218
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/* Platform specific system counter */
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
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#endif /* PLAT_SOCFPGA_DEF_H */
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@ -9,14 +9,15 @@
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#define PLAT_SOCFPGA_DEF_H
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#include <platform_def.h>
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#include <lib/utils_def.h>
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#include "n5x_system_manager.h"
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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@ -35,10 +36,10 @@
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#define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000)
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#define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000)
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#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
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#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
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#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
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#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
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#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
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#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
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#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
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#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
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/*******************************************************************************
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@ -65,17 +66,17 @@
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#define DEVICE4_BASE (0x2000000000)
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#define DEVICE4_SIZE (0x0100000000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe1b000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe1b000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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/*******************************************************************************
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* WDT related constants
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@ -85,19 +86,19 @@
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/*******************************************************************************
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* GIC related constants
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******************************************************************************/
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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/*******************************************************************************
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* SDMMC related pointer function
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******************************************************************************/
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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/*******************************************************************************
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* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
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@ -106,6 +107,6 @@
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#define L2_RESET_DONE_REG 0xFFD12218
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/* Platform specific system counter */
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
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#endif /* PLAT_SOCFPGA_DEF_H */
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@ -8,14 +8,15 @@
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#define PLAT_SOCFPGA_DEF_H
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#include <platform_def.h>
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#include <lib/utils_def.h>
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#include "s10_system_manager.h"
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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@ -63,17 +64,17 @@
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#define DEVICE4_BASE (0x2000000000)
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#define DEVICE4_SIZE (0x0100000000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe2b000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe2b000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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/*******************************************************************************
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* WDT related constants
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@ -83,19 +84,19 @@
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/*******************************************************************************
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* GIC related constants
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******************************************************************************/
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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/*******************************************************************************
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* SDMMC related pointer function
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******************************************************************************/
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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/*******************************************************************************
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* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
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@ -104,7 +105,7 @@
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#define L2_RESET_DONE_REG 0xFFD12218
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/* Platform specific system counter */
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
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#endif /* PLATSOCFPGA_DEF_H */
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