Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 17:44:19 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(intel): update Agilex5 BL2 init flow and other misc changes

Browse source 
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2024-08-27 00:01:51 +08:00 • committed by Tang Sieu Mun
parent ce21a1a909
commit b3d2850842
12 changed files with 66 additions and 35 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -19,6 +19,7 @@
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
#define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000

44
plat/intel/soc/agilex5/bl2_plat_setup.c
View file

@ -24,6 +24,7 @@
#include "agilex5_memory_controller.h"
#include "agilex5_mmc.h"
#include "agilex5_pinmux.h"
#include "agilex5_power_manager.h"
#include "agilex5_system_manager.h"
#include "ccu/ncore_ccu.h"
#include "combophy/combophy.h"
@ -71,16 +72,39 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
u_register_t x2, u_register_t x4)
{
static console_t console;
handoff reverse_handoff_ptr;
handoff reverse_handoff_ptr = { 0 };
generic_delay_timer_init();
config_clkmgr_handoff(&reverse_handoff_ptr);
mailbox_init();
/* Enable nonsecure access for peripherals and other misc components */
enable_nonsecure_access();
/* Bring all the required peripherals out of reset */
deassert_peripheral_reset();
/*
* Initialize the UART console early in BL2 EL3 boot flow to get
* the error/notice messages wherever required.
*/
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
/* Generic delay timer init */
generic_delay_timer_init();
socfpga_delay_timer_init();
/* Get the handoff data */
if ((socfpga_get_handoff(&reverse_handoff_ptr)) != 0) {
ERROR("BL2: Failed to get the correct handoff data\n");
panic();
}
config_clkmgr_handoff(&reverse_handoff_ptr);
/* Configure power manager PSS SRAM power gate */
config_pwrmgr_handoff(&reverse_handoff_ptr);
/* Initialize the mailbox to enable communication between HPS and SDM */
mailbox_init();
/* DDR and IOSSM driver init */
agilex5_ddr_init(&reverse_handoff_ptr);
@ -88,16 +112,10 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
ERROR("Combo Phy initialization failed\n");
}
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
/* Store magic number */
// TODO: Temp workaround to ungate testing
// mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ);
/* Enable FPGA bridges as required */
if (!intel_mailbox_is_fpga_not_ready()) {
socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
FPGA2SOC_MASK | F2SDRAM0_MASK);
FPGA2SOC_MASK | F2SDRAM0_MASK);
}
}

7
plat/intel/soc/agilex5/bl31_plat_setup.c
View file

@ -58,9 +58,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
PLAT_BAUDRATE, &console);
init_ncore_ccu();
setup_smmu_stream_id();
/*
@ -191,8 +190,8 @@ void bl31_plat_arch_setup(void)
uint32_t boot_core = 0x00;
uint32_t cpuid = 0x00;
cpuid = read_mpidr();
boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00);
cpuid = MPIDR_AFFLVL1_VAL(read_mpidr());
boot_core = ((mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00) >> 10);
NOTICE("BL31: Boot Core = %x\n", boot_core);
NOTICE("BL31: CPU ID = %x\n", cpuid);
INFO("BL31: Invalidate Data cache\n");

5
plat/intel/soc/agilex5/include/agilex5_power_manager.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -77,7 +78,5 @@
#define AGX5_PWRMGR_PSS_STAT_BUSY_E_BUSY 0x0
#define AGX5_PWRMGR_PSS_STAT_BUSY(x) (((x) & 0x000000FF) >> 0)
int pss_sram_power_off(handoff *hoff_ptr);
int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff);
void config_pwrmgr_handoff(handoff *hoff_ptr);
#endif

8
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -23,13 +23,14 @@
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_L2_RESET_REQ 0xB007C0DE
#define PLAT_TIMER_BASE_ADDR 0x10D01000
/* System Counter */
/* TODO: Update back to 400MHz.
* This shall be updated to read from L4 clock instead of hardcoded.
*/
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000)
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000
@ -88,11 +89,10 @@
#define GIC_SIZE (0x00100000)
#define BL2_BASE (0x00000000)
#define BL2_LIMIT (0x0002b000)
#define BL2_LIMIT (0x0007E000)
#define BL31_BASE (0x80000000)
#define BL31_LIMIT (0x82000000)
/*******************************************************************************
* UART related constants
******************************************************************************/

15
plat/intel/soc/agilex5/soc/agilex5_pinmux.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -195,11 +196,15 @@ void config_pinmux(handoff *hoff_ptr)
{
unsigned int i;
mmio_write_32(PINMUX_HANDOFF_CONFIG_ADDR, PINMUX_HANDOFF_CONFIG_VAL);
for (i = 0; i < PINMUX_HANDOFF_ARRAY_SIZE(hoff_ptr->pinmux_sel_array); i += 2) {
mmio_write_32(AGX5_PINMUX_PIN0SEL +
hoff_ptr->pinmux_sel_array[i],
hoff_ptr->pinmux_sel_array[i + 1]);
/*
* Configure the FPGA use.
* The actual generic handoff contains extra 4 elements, and these 4 elements
* are not applicable to the Agilex5 platform. Writing these extra 4 elements
* will cause the system to crash, so let's avoid writing them here.
*/
for (i = 0; i < (ARRAY_SIZE(hoff_ptr->pinmux_fpga_array) - 4); i += 2) {
mmio_write_32(AGX5_PINMUX_EMAC0_USEFPGA + hoff_ptr->pinmux_fpga_array[i],
hoff_ptr->pinmux_fpga_array[i+1]);
}
config_fpgaintf_mod();

2
plat/intel/soc/common/soc/socfpga_reset_manager.c
View file

@ -76,7 +76,7 @@ void deassert_peripheral_reset(void)
RSTMGR_FIELD(PER0, DMAIF6) |
RSTMGR_FIELD(PER0, DMAIF7));
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
#if (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5)
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_FIELD(BRG, MPFE));
#endif

6
plat/intel/soc/common/socfpga_delay_timer.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,7 +11,6 @@
#include <lib/mmio.h>
#include "socfpga_plat_def.h"
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
#include "agilex_clock_manager.h"
#elif PLATFORM_MODEL == PLAT_SOCFPGA_N5X
@ -19,7 +19,7 @@
#include "s10_clock_manager.h"
#endif
#define SOCFPGA_GLOBAL_TIMER 0xffd01000
#define SOCFPGA_GLOBAL_TIMER PLAT_TIMER_BASE_ADDR
#define SOCFPGA_GLOBAL_TIMER_EN 0x3
static timer_ops_t plat_timer_ops;
@ -44,7 +44,6 @@ void socfpga_delay_timer_init_args(void)
plat_timer_ops.clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ;
timer_init(&plat_timer_ops);
}
void socfpga_delay_timer_init(void)
@ -54,5 +53,4 @@ void socfpga_delay_timer_init(void)
asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN));
asm volatile("msr cntp_tval_el0, %0" : : "r" (~0));
}

7
plat/intel/soc/common/socfpga_image_load.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,7 +13,13 @@
******************************************************************************/
void plat_flush_next_bl_params(void)
{
/*
* We cannot flush these descriptors on the Agilex5 platform,
* since the BL2 runs on the OCRAM and this OCRAM is not cache coherent.
*/
#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
flush_bl_params_desc();
#endif
}
/*******************************************************************************

2
plat/intel/soc/n5x/include/n5x_clock_manager.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,7 +10,6 @@
/* MACRO DEFINITION */
#define SOCFPGA_GLOBAL_TIMER 0xffd01000
#define SOCFPGA_GLOBAL_TIMER_EN 0x3
#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16)

2
plat/intel/soc/n5x/include/socfpga_plat_def.h
View file

@ -1,6 +1,7 @@
/*
* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -18,6 +19,7 @@
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
#define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000

2
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,6 +18,7 @@
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
#define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000