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Merge "feat(intel): add build option for boot source" into integration

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This commit is contained in:
Mark Dykes 2024-10-28 23:08:07 +01:00 • committed by TrustedFirmware Code Review
commit 2c878eb6c7
10 changed files with 96 additions and 7 deletions
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1
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -15,7 +15,6 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
/* 1 = Flush cache, 0 = No cache flush.
* Default for Agilex is No cache flush.
* For Agilex FP8, set to Flush cache.

18
plat/intel/soc/agilex/platform.mk
View file

@ -88,6 +88,24 @@ $(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
# Configs for Boot Source
SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
SOCFPGA_BOOT_SOURCE_QSPI ?= 0
SOCFPGA_BOOT_SOURCE_NAND ?= 0
$(eval $(call assert_booleans,\
$(sort \
SOCFPGA_BOOT_SOURCE_SDMMC \
SOCFPGA_BOOT_SOURCE_QSPI \
SOCFPGA_BOOT_SOURCE_NAND \
)))
$(eval $(call add_defines,\
$(sort \
SOCFPGA_BOOT_SOURCE_SDMMC \
SOCFPGA_BOOT_SOURCE_QSPI \
SOCFPGA_BOOT_SOURCE_NAND \
)))
# Configs for VAB Authentication
SOCFPGA_SECURE_VAB_AUTH := 0
$(eval $(call assert_boolean,SOCFPGA_SECURE_VAB_AUTH))

1
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -16,7 +16,6 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
/* 1 = Flush cache, 0 = No cache flush.
* Default for Agilex5 is Cache flush.
*/

18
plat/intel/soc/agilex5/platform.mk
View file

@ -113,6 +113,24 @@ $(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
# Configs for Boot Source
SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
SOCFPGA_BOOT_SOURCE_QSPI ?= 0
SOCFPGA_BOOT_SOURCE_NAND ?= 0
$(eval $(call assert_booleans,\
$(sort \
SOCFPGA_BOOT_SOURCE_SDMMC \
SOCFPGA_BOOT_SOURCE_QSPI \
SOCFPGA_BOOT_SOURCE_NAND \
)))
$(eval $(call add_defines,\
$(sort \
SOCFPGA_BOOT_SOURCE_SDMMC \
SOCFPGA_BOOT_SOURCE_QSPI \
SOCFPGA_BOOT_SOURCE_NAND \
)))
# Configs for VAB Authentication
SOCFPGA_SECURE_VAB_AUTH := 0
$(eval $(call assert_boolean,SOCFPGA_SECURE_VAB_AUTH))

12
plat/intel/soc/common/include/platform_def.h
View file

@ -22,6 +22,18 @@
#define PLAT_SOCFPGA_AGILEX5 4
#define SIMICS_RUN 1
#define MAX_IO_MTD_DEVICES U(1)
/* Boot Source configuration
* TODO: Shall consider "assert_numeric" in the future
*/
#if SOCFPGA_BOOT_SOURCE_NAND
#define BOOT_SOURCE BOOT_SOURCE_NAND
#elif SOCFPGA_BOOT_SOURCE_SDMMC
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
#elif SOCFPGA_BOOT_SOURCE_QSPI
#define BOOT_SOURCE BOOT_SOURCE_QSPI
#else
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
#endif
/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
#define PLAT_CPU_RELEASE_ADDR 0xffd12210

4
plat/intel/soc/common/include/socfpga_private.h
View file

@ -24,8 +24,8 @@ typedef enum {
BOOT_SOURCE_FPGA = 0,
BOOT_SOURCE_SDMMC,
BOOT_SOURCE_NAND,
BOOT_SOURCE_RSVD,
BOOT_SOURCE_QSPI
BOOT_SOURCE_QSPI,
BOOT_SOURCE_RSVD
} boot_source_type;
/*******************************************************************************

1
plat/intel/soc/n5x/include/socfpga_plat_def.h
View file

@ -15,7 +15,6 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT

25
plat/intel/soc/n5x/platform.mk
View file

@ -1,5 +1,6 @@
#
# Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
# Copyright (c) 2024, Altera Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -46,8 +47,30 @@ BL31_SOURCES += \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c
# Don't have the Linux kernel as a BL33 image by default
ARM_LINUX_KERNEL_AS_BL33 := 0
$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
# Configs for Boot Source
SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
SOCFPGA_BOOT_SOURCE_QSPI ?= 0
SOCFPGA_BOOT_SOURCE_NAND ?= 0
$(eval $(call assert_booleans,\
$(sort \
SOCFPGA_BOOT_SOURCE_SDMMC \
SOCFPGA_BOOT_SOURCE_QSPI \
SOCFPGA_BOOT_SOURCE_NAND \
)))
$(eval $(call add_defines,\
$(sort \
SOCFPGA_BOOT_SOURCE_SDMMC \
SOCFPGA_BOOT_SOURCE_QSPI \
SOCFPGA_BOOT_SOURCE_NAND \
)))
PROGRAMMABLE_RESET_ADDRESS := 0
RESET_TO_BL2 := 1
BL2_INV_DCACHE := 0

1
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -14,7 +14,6 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT

22
plat/intel/soc/stratix10/platform.mk
View file

@ -78,8 +78,30 @@ BL31_SOURCES += \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c
# Don't have the Linux kernel as a BL33 image by default
ARM_LINUX_KERNEL_AS_BL33 := 0
$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
# Configs for Boot Source
SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
SOCFPGA_BOOT_SOURCE_QSPI ?= 0
SOCFPGA_BOOT_SOURCE_NAND ?= 0
$(eval $(call assert_booleans,\
$(sort \
SOCFPGA_BOOT_SOURCE_SDMMC \
SOCFPGA_BOOT_SOURCE_QSPI \
SOCFPGA_BOOT_SOURCE_NAND \
)))
$(eval $(call add_defines,\
$(sort \
SOCFPGA_BOOT_SOURCE_SDMMC \
SOCFPGA_BOOT_SOURCE_QSPI \
SOCFPGA_BOOT_SOURCE_NAND \
)))
PROGRAMMABLE_RESET_ADDRESS := 0
RESET_TO_BL2 := 1
USE_COHERENT_MEM := 1