fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the starting of the DDR is from 0x0000 0000. And if there is
no NS_image_offset set, the Jenkins is not able to acquire the correct
address offset to boot up the system. However, in the direct OS boot,
there is no issue as the user shall always include the address offset
during the compilation phase. Otherwise, the code shall execute the
default address offset. Besides that, this also provides the
flexibility to user to customize their SoC design by not restricted
to the default address.

SDMMC block size. It was changed due to the need when boot to Linux.
Kernel.itb size is big thus we have to increase the available reading
block size. Otherwise for normal U-boot and Zephyr it shall not be
reading a big block size to avoid "garbage" data.

Change-Id: I1c2a22db28bf0ada734563e40efd4f5749951273
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

include/drivers/cadence/cdns_sdmmc.h

@@ -281,7 +281,6 @@
 								(SDMMC_CDN_##_reg))
 
 /* MMC Peripheral Definition */
-#define SOCFPGA_MMC_BLOCK_SIZE		U(8192)
 #define SOCFPGA_MMC_BLOCK_MASK		(SOCFPGA_MMC_BLOCK_SIZE - U(1))
 #define SOCFPGA_MMC_BOOT_CLK_RATE	(400 * 1000)
 #define MMC_RESPONSE_NONE			0

plat/intel/soc/agilex/bl31_plat_setup.c

@@ -133,8 +133,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	 * Tell BL31 where the non-trusted software image
 	 * is located and the entry state information
 	 */
+# if ARM_LINUX_KERNEL_AS_BL33
 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 	bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+#endif
 
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 }

plat/intel/soc/agilex/include/socfpga_plat_def.h

@@ -29,6 +29,13 @@
 #define CAD_QSPIDATA_OFST			0xff900000
 #define CAD_QSPI_OFFSET				0xff8d2000
 
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE			U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE			U(8192)
+# endif
+
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000
 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)

plat/intel/soc/agilex5/include/socfpga_plat_def.h

@@ -41,6 +41,13 @@
 #define CAD_QSPIDATA_OFST					0x10900000
 #define CAD_QSPI_OFFSET						0x108d2000
 
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE					U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE					U(8192)
+# endif
+
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE				0x1c000000
 #define SOCFPGA_F2SDRAMMGR_REG_BASE				0x18001000

plat/intel/soc/common/socfpga_storage.c

@@ -22,16 +22,21 @@
 #include <drivers/partition/partition.h>
 #include <lib/mmio.h>
 #include <tools_share/firmware_image_package.h>
-
 #include "drivers/sdmmc/sdmmc.h"
 #include "socfpga_private.h"
 #include "socfpga_ros.h"
 
 
 #define PLAT_FIP_BASE		(0)
+# if ARM_LINUX_KERNEL_AS_BL33
 #define PLAT_FIP_MAX_SIZE	(0x8000000)
 #define PLAT_MMC_DATA_BASE	(0x10000000)
 #define PLAT_MMC_DATA_SIZE	(0x100000)
+# else
+#define PLAT_FIP_MAX_SIZE	(0x1000000)
+#define PLAT_MMC_DATA_BASE	(0xffe3c000)
+#define PLAT_MMC_DATA_SIZE	(0x2000)
+# endif
 
 static const io_dev_connector_t *fip_dev_con;
 static const io_dev_connector_t *boot_dev_con;

plat/intel/soc/n5x/include/socfpga_plat_def.h

@@ -29,6 +29,13 @@
 #define CAD_QSPIDATA_OFST			0xff900000
 #define CAD_QSPI_OFFSET				0xff8d2000
 
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE			U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE			U(8192)
+# endif
+
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		U(0xf7000000)
 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)

plat/intel/soc/stratix10/include/socfpga_plat_def.h

@@ -28,6 +28,13 @@
 #define CAD_QSPIDATA_OFST			0xff900000
 #define CAD_QSPI_OFFSET				0xff8d2000
 
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE			U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE			U(8192)
+# endif
+
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000
 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)