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feat(intel): increase bl2 size limit

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There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2 image has exceeded its limits.

Change-Id: I7542f5ea001542450695d48e8126bcca8728d76a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
This commit is contained in:
Jit Loon Lim 2023-09-27 11:02:45 +08:00
parent 93823fb6ec
commit 2d46b2e461
3 changed files with 3 additions and 3 deletions
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2
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -65,7 +65,7 @@
#define DEVICE4_SIZE (0x0100000000)
#define BL2_BASE (0xffe00000)
#define BL2_LIMIT (0xffe1b000)
#define BL2_LIMIT (0xffe2b000)
#define BL31_BASE (0x1000)
#define BL31_LIMIT (0x81000)

2
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -83,7 +83,7 @@
#define GIC_SIZE (0x00100000)
#define BL2_BASE (0x00000000)
#define BL2_LIMIT (0x0001b000)
#define BL2_LIMIT (0x0002b000)
#define BL31_BASE (0x80000000)
#define BL31_LIMIT (0x82000000)

2
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -64,7 +64,7 @@
#define DEVICE4_SIZE (0x0100000000)
#define BL2_BASE (0xffe00000)
#define BL2_LIMIT (0xffe1b000)
#define BL2_LIMIT (0xffe2b000)
#define BL31_BASE (0x1000)
#define BL31_LIMIT (0x81000)