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fix(intel): fix hardcoded mpu frequency ticks

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This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Jit Loon Lim 2023-07-07 17:15:26 +08:00
parent 93823fb6ec
commit 150d2be0d2
14 changed files with 113 additions and 24 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
plat/intel/soc/agilex/include/agilex_clock_manager.h
View file

@ -129,5 +129,6 @@ uint32_t get_uart_clk(void);
uint32_t get_mmc_clk(void);
uint32_t get_mpu_clk(void);
uint32_t get_cpu_clk(void);
uint32_t get_mpu_periph_clk(void);
#endif

4
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -84,7 +84,7 @@
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/*******************************************************************************
@ -100,6 +100,6 @@
#define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk()
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
#endif /* PLAT_SOCFPGA_DEF_H */

15
plat/intel/soc/agilex/soc/agilex_clock_manager.c
View file

@ -407,3 +407,18 @@ uint32_t get_cpu_clk(void)
return cpu_clk;
}
/* Return mpu_periph_clk clock frequency */
uint32_t get_mpu_periph_clk(void)
{
uint32_t mpu_periph_clk = 0;
/* mpu_periph_clk is mpu_clk, via a static /4 divider */
mpu_periph_clk = (get_mpu_clk()/4)/PLAT_HZ_CONVERT_TO_MHZ;
return mpu_periph_clk;
}
/* Return mpu_periph_clk tick */
unsigned int plat_get_syscnt_freq2(void)
{
return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
}

1
plat/intel/soc/agilex5/platform.mk
View file

@ -83,6 +83,7 @@ BL31_SOURCES += \
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_psci_common.c \
plat/intel/soc/agilex5/bl31_plat_setup.c \
plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \
plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_sip_svc.c \

7
plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
View file

@ -14,6 +14,7 @@
#include "agilex5_clock_manager.h"
#include "agilex5_system_manager.h"
#include "socfpga_handoff.h"
#include "socfpga_system_manager.h"
uint32_t wait_pll_lock(void)
{
@ -251,3 +252,9 @@ uint32_t get_mmc_clk(void)
return mmc_clk;
}
/* Return mpu_periph_clk tick */
unsigned int plat_get_syscnt_freq2(void)
{
return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
}

6
plat/intel/soc/common/aarch64/platform_common.c
View file

@ -11,12 +11,6 @@
#include "socfpga_private.h"
unsigned int plat_get_syscnt_freq2(void)
{
return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
}
unsigned long socfpga_get_ns_image_entrypoint(void)
{
return PLAT_NS_IMAGE_OFFSET;

1
plat/intel/soc/common/include/socfpga_private.h
View file

@ -7,7 +7,6 @@
#ifndef SOCFPGA_PRIVATE_H
#define SOCFPGA_PRIVATE_H
#include "socfpga_plat_def.h"
#define EMMC_DESC_SIZE (1<<20)

2
plat/intel/soc/common/socfpga_delay_timer.c
View file

@ -52,8 +52,6 @@ void socfpga_delay_timer_init(void)
socfpga_delay_timer_init_args();
mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
NOTICE("BL31 CLK freq = %d MHz\n", PLAT_SYS_COUNTER_FREQ_IN_MHZ);
asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN));
asm volatile("msr cntp_tval_el0, %0" : : "r" (~0));

8
plat/intel/soc/n5x/include/n5x_clock_manager.h
View file

@ -4,10 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CLOCKMANAGER_H
#define CLOCKMANAGER_H
#ifndef N5X_SOCFPGA_CLOCKMANAGER_H
#define N5X_SOCFPGA_CLOCKMANAGER_H
#include "socfpga_handoff.h"
/* MACRO DEFINITION */
#define SOCFPGA_GLOBAL_TIMER 0xffd01000
@ -56,5 +55,6 @@ uint64_t get_l4_clk(void);
uint32_t get_clk_freq(uint32_t psrc_reg);
uint32_t get_mpu_clk(void);
uint32_t get_cpu_clk(void);
uint32_t get_mpu_periph_clk(void);
#endif
#endif /* N5X_SOCFPGA_CLOCKMANAGER_H */

6
plat/intel/soc/n5x/include/socfpga_plat_def.h
View file

@ -8,8 +8,8 @@
#ifndef PLAT_SOCFPGA_DEF_H
#define PLAT_SOCFPGA_DEF_H
#include "n5x_system_manager.h"
#include <platform_def.h>
#include "n5x_system_manager.h"
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
@ -85,7 +85,7 @@
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/*******************************************************************************
@ -101,6 +101,6 @@
#define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk()
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
#endif /* PLAT_SOCFPGA_DEF_H */

18
plat/intel/soc/n5x/soc/n5x_clock_manager.c
View file

@ -12,8 +12,7 @@
#include "n5x_clock_manager.h"
#include "n5x_system_manager.h"
#include "socfpga_handoff.h"
uint64_t clk_get_pll_output_hz(void)
{
@ -155,3 +154,18 @@ uint32_t get_cpu_clk(void)
return cpu_clk;
}
/* Return mpu_periph_clk clock frequency */
uint32_t get_mpu_periph_clk(void)
{
uint32_t mpu_periph_clk = 0;
/* mpu_periph_clk is mpu_clk, via a static /4 divider */
mpu_periph_clk = (get_mpu_clk()/4)/PLAT_HZ_CONVERT_TO_MHZ;
return mpu_periph_clk;
}
/* Return mpu_periph_clk tick */
unsigned int plat_get_syscnt_freq2(void)
{
return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
}

2
plat/intel/soc/stratix10/include/s10_clock_manager.h
View file

@ -96,6 +96,6 @@ uint32_t get_uart_clk(void);
uint32_t get_mmc_clk(void);
uint32_t get_l3_clk(uint32_t ref_clk);
uint32_t get_ref_clk(uint32_t pllglob);
uint32_t get_cpu_clk(void);
uint32_t get_mpu_periph_clk(void);
#endif

4
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -83,7 +83,7 @@
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/*******************************************************************************
@ -99,7 +99,7 @@
#define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk()
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
#endif /* PLATSOCFPGA_DEF_H */

62
plat/intel/soc/stratix10/soc/s10_clock_manager.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -230,6 +230,40 @@ uint32_t get_ref_clk(uint32_t pllglob)
return ref_clk;
}
/* Calculate clock frequency based on parameter */
uint32_t get_clk_freq(uint32_t psrc_reg, uint32_t main_pllc, uint32_t per_pllc)
{
uint32_t clk_psrc, ref_clk;
uint32_t pllc_reg, pllc_div, pllglob_reg;
clk_psrc = mmio_read_32(ALT_CLKMGR_MAINPLL + psrc_reg);
switch (ALT_CLKMGR_PSRC(clk_psrc)) {
case ALT_CLKMGR_SRC_MAIN:
pllc_reg = ALT_CLKMGR_MAINPLL + main_pllc;
pllglob_reg = ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB;
break;
case ALT_CLKMGR_SRC_PER:
pllc_reg = ALT_CLKMGR_PERPLL + per_pllc;
pllglob_reg = ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB;
break;
default:
return 0;
}
ref_clk = get_ref_clk(mmio_read_32(pllglob_reg));
pllc_div = mmio_read_32(pllc_reg) & 0xff;
if (pllc_div != 0) {
ref_clk = (ref_clk / pllc_div) / (clk_psrc + 1);
return ref_clk;
} else {
VERBOSE("PLL DIV is 0\n");
return 0;
}
}
/* Calculate L3 interconnect main clock */
uint32_t get_l3_clk(uint32_t ref_clk)
{
@ -308,6 +342,17 @@ uint32_t get_mmc_clk(void)
return mmc_clk;
}
/* Return MPU clock */
uint32_t get_mpu_clk(void)
{
uint32_t mpu_clk;
mpu_clk = get_clk_freq(ALT_CLKMGR_MAINPLL_NOCCLK, ALT_CLKMGR_MAINPLL_PLLC0,
ALT_CLKMGR_PERPLL_PLLC0);
return mpu_clk;
}
/* Get cpu freq clock */
uint32_t get_cpu_clk(void)
{
@ -320,3 +365,18 @@ uint32_t get_cpu_clk(void)
return cpu_clk;
}
/* Return mpu_periph_clk clock frequency */
uint32_t get_mpu_periph_clk(void)
{
uint32_t mpu_periph_clk = 0;
/* mpu_periph_clk is mpu_clk, via a static /4 divider */
mpu_periph_clk = (get_mpu_clk()/4)/PLAT_HZ_CONVERT_TO_MHZ;
return mpu_periph_clk;
}
/* Return mpu_periph_clk tick */
unsigned int plat_get_syscnt_freq2(void)
{
return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
}