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fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset. Issue happen where Agilex5 hardware does not support the caches flush. Thus software workaround is needed. Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang
parent
2752c2a849
commit
7ac7dadb55
8 changed files with 124 additions and 3 deletions
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@ -16,6 +16,11 @@
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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/* 1 = Flush cache, 0 = No cache flush.
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* Default for Agilex is No cache flush.
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* For Agilex FP8, set to Flush cache.
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*/
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#define CACHE_FLUSH 0
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#define PLAT_PRIMARY_CPU 0
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#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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@ -17,6 +17,10 @@
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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/* 1 = Flush cache, 0 = No cache flush.
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* Default for Agilex5 is Cache flush.
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*/
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#define CACHE_FLUSH 1
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#define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */
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#define XLAT_TABLES_V2 U(1)
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#define PLAT_PRIMARY_CPU_A55 0x000
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@ -1,5 +1,7 @@
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/*
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* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -19,6 +21,7 @@
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl plat_secondary_cpus_bl31_entry
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.globl invalidate_cache_low_el
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.globl plat_get_my_entrypoint
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@ -213,3 +216,18 @@ func plat_secondary_cpus_bl31_entry
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_exception_vectors=runtime_exceptions \
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_pie_fixup_size=BL31_LIMIT - BL31_BASE
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endfunc plat_secondary_cpus_bl31_entry
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/* --------------------------------------------------------
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* Invalidate for NS EL2 and EL1
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* --------------------------------------------------------
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*/
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func invalidate_cache_low_el
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mrs x0,SCR_EL3
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orr x1,x0,#SCR_NS_BIT
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msr SCR_EL3, x1
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isb
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tlbi ALLE2
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dsb sy
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tlbi ALLE1
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dsb sy
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endfunc invalidate_cache_low_el
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@ -1,10 +1,12 @@
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/*
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <errno.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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@ -16,7 +18,24 @@
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uint32_t poll_active_bit(uint32_t dir);
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#define SMMU_DMI 1
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#define SMMU_DMI 1
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#define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_NOC_REG_BASE + 0x7340
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#define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_NOC_REG_BASE + 0x7344
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#define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0)
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#define MAX_DISTRIBUTED_MEM_INTERFACE 2
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#define FLUSH_ALL_ENTRIES 0x4
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#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16)
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#define ARRAY_ID_TAG 0x0
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#define ARRAY_ID_DATA 0x1
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#define CACHE_OPERATION_DONE BIT(0)
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#define TIMEOUT_200MS 200
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#define __bf_shf(x) (__builtin_ffsll(x) - 1)
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#define FIELD_PREP(_mask, _val) \
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({ \
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((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
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})
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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ncore_ccu_reg_t ncore_ccu_modules[] = {
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@ -632,3 +651,61 @@ void setup_smmu_stream_id(void)
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mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN1), ENABLE_STREAMID);
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mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN2), ENABLE_STREAMID);
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}
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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/* TODO: Temp added this here*/
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static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
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{
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int time_out = delay_ms;
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while (time_out-- > 0) {
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if ((mmio_read_32(addr) & mask) == match) {
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return 0;
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}
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udelay(1000);
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}
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return -ETIMEDOUT;
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}
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int flush_l3_dcache(void)
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{
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int i;
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int ret = 0;
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/* Flushing all entries in CCU system memory cache */
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for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) {
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mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
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FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG),
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(uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
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/* Wait for cache maintenance operation done */
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ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR +
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(i * 0x1000)), CACHE_OPERATION_DONE,
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CACHE_OPERATION_DONE, TIMEOUT_200MS);
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if (ret != 0) {
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VERBOSE("%s: Timeout while waiting for flushing tag in DMI%d done\n",
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__func__, i);
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return ret;
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}
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mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
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FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA),
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(uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
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/* Wait for cache maintenance operation done */
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ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR +
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(i * 0x1000)), CACHE_OPERATION_DONE,
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CACHE_OPERATION_DONE, TIMEOUT_200MS);
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if (ret != 0) {
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VERBOSE("%s: Timeout while waiting for flushing data in DMI%d done\n",
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__func__, i);
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}
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}
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return ret;
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}
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#endif
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -452,5 +453,6 @@ typedef struct coh_ss_id {
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uint32_t init_ncore_ccu(void);
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void ncore_enable_ocram_firewall(void);
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void setup_smmu_stream_id(void);
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int flush_l3_dcache(void);
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#endif
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -64,4 +65,6 @@ unsigned long socfpga_get_ns_image_entrypoint(void);
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void plat_secondary_cpus_bl31_entry(void);
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void invalidate_cache_low_el(void);
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#endif /* SOCFPGA_PRIVATE_H */
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@ -17,8 +17,10 @@
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include "ccu/ncore_ccu.h"
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#include "socfpga_mailbox.h"
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#include "socfpga_plat_def.h"
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#include "socfpga_private.h"
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#include "socfpga_reset_manager.h"
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#include "socfpga_sip_svc.h"
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#include "socfpga_system_manager.h"
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@ -190,6 +192,14 @@ static void __dead2 socfpga_system_reset(void)
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if (intel_rsu_update_address) {
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mailbox_rsu_update(addr_buf);
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} else {
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#if CACHE_FLUSH
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/* ATF Flush and Invalidate Cache */
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dcsw_op_all(DCCISW);
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invalidate_cache_low_el();
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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flush_l3_dcache();
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#endif
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#endif
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mailbox_reset_cold();
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}
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@ -1,6 +1,7 @@
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#
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# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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# Copyright (c) 2024, Altera Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -26,6 +27,7 @@ PLAT_BL_COMMON_SOURCES := \
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lib/xlat_tables/xlat_tables_common.c \
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plat/intel/soc/common/aarch64/platform_common.c \
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plat/intel/soc/common/aarch64/plat_helpers.S \
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plat/intel/soc/common/drivers/ccu/ncore_ccu.c \
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plat/intel/soc/common/socfpga_delay_timer.c \
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plat/intel/soc/common/soc/socfpga_firewall.c
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