mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-26 23:04:50 +00:00
7ac7dadb55
This fix is to flush and invalidate the caches before cold reset. Issue happen where Agilex5 hardware does not support the caches flush. Thus software workaround is needed. Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
299 lines
9.3 KiB
C
299 lines
9.3 KiB
C
/*
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* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#ifndef GICV3_SUPPORT_GIC600
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#include <drivers/arm/gicv2.h>
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#else
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#include <drivers/arm/gicv3.h>
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#endif
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include "ccu/ncore_ccu.h"
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#include "socfpga_mailbox.h"
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#include "socfpga_plat_def.h"
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#include "socfpga_private.h"
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#include "socfpga_reset_manager.h"
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#include "socfpga_sip_svc.h"
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#include "socfpga_system_manager.h"
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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void socfpga_wakeup_secondary_cpu(unsigned int cpu_id);
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extern void plat_secondary_cold_boot_setup(void);
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#endif
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/*******************************************************************************
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* plat handler called when a CPU is about to enter standby.
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******************************************************************************/
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void socfpga_cpu_standby(plat_local_state_t cpu_state)
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{
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/*
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* Enter standby state
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* dsb is good practice before using wfi to enter low power states
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*/
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VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
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dsb();
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wfi();
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}
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/*******************************************************************************
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* plat handler called when a power domain is about to be turned on. The
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* mpidr determines the CPU to be turned on.
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******************************************************************************/
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int socfpga_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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/* TODO: Add in CPU FUSE from SDM */
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#else
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uint32_t psci_boot = 0x00;
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VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
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#endif
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if (cpu_id == -1)
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return PSCI_E_INTERN_FAIL;
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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if (cpu_id == 0x00) {
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psci_boot = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8));
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psci_boot |= 0x80000; /* bit 19 */
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mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8), psci_boot);
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}
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mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
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#endif
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/* release core reset */
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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bl31_plat_set_secondary_cpu_entrypoint(cpu_id);
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#else
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mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
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mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
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#endif
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* plat handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void socfpga_pwr_domain_off(const psci_power_state_t *target_state)
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{
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* Prevent interrupts from spuriously waking up this cpu */
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#ifdef GICV3_SUPPORT_GIC600
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gicv3_cpuif_disable(plat_my_core_pos());
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#else
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gicv2_cpuif_disable();
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#endif
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}
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/*******************************************************************************
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* plat handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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unsigned int cpu_id = plat_my_core_pos();
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#endif
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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/* assert core reset */
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mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
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#endif
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}
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/*******************************************************************************
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* plat handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void socfpga_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* Enable the gic cpu interface */
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#ifdef GICV3_SUPPORT_GIC600
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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#else
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/* Program the gic per-cpu distributor or re-distributor interface */
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gicv2_pcpu_distif_init();
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gicv2_set_pe_target_mask(plat_my_core_pos());
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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#endif
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}
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/*******************************************************************************
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* plat handler called when a power domain has just been powered on after
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* having been suspended earlier. The target_state encodes the low power state
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* that each level has woken up from.
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* TODO: At the moment we reuse the on finisher and reinitialize the secure
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* context. Need to implement a separate suspend finisher.
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******************************************************************************/
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void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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unsigned int cpu_id = plat_my_core_pos();
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#endif
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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/* release core reset */
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mmio_clrbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
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#endif
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}
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/*******************************************************************************
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* plat handlers to shutdown/reboot the system
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******************************************************************************/
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static void __dead2 socfpga_system_off(void)
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{
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wfi();
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ERROR("System Off: operation not handled.\n");
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panic();
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}
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extern uint64_t intel_rsu_update_address;
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static void __dead2 socfpga_system_reset(void)
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{
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uint32_t addr_buf[2];
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memcpy_s(addr_buf, sizeof(intel_rsu_update_address),
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&intel_rsu_update_address, sizeof(intel_rsu_update_address));
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if (intel_rsu_update_address) {
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mailbox_rsu_update(addr_buf);
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} else {
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#if CACHE_FLUSH
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/* ATF Flush and Invalidate Cache */
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dcsw_op_all(DCCISW);
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invalidate_cache_low_el();
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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flush_l3_dcache();
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#endif
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#endif
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mailbox_reset_cold();
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}
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while (1)
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wfi();
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}
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static int socfpga_system_reset2(int is_vendor, int reset_type,
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u_register_t cookie)
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{
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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mailbox_reset_warm(reset_type);
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#else
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if (cold_reset_for_ecc_dbe()) {
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mailbox_reset_cold();
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}
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#endif
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/* disable cpuif */
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#ifdef GICV3_SUPPORT_GIC600
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gicv3_cpuif_disable(plat_my_core_pos());
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#else
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gicv2_cpuif_disable();
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#endif
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/* Store magic number */
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mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS);
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/* Increase timeout */
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mmio_write_32(SOCFPGA_RSTMGR(HDSKTIMEOUT), 0xffffff);
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/* Enable handshakes */
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET);
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#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
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/* Reset L2 module */
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mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100);
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#endif
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while (1)
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wfi();
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/* Should not reach here */
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return 0;
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}
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int socfpga_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
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return PSCI_E_SUCCESS;
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}
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int socfpga_validate_ns_entrypoint(unsigned long ns_entrypoint)
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{
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VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
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return PSCI_E_SUCCESS;
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}
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void socfpga_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
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}
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/*******************************************************************************
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* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
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* platform layer will take care of registering the handlers with PSCI.
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******************************************************************************/
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const plat_psci_ops_t socfpga_psci_pm_ops = {
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.cpu_standby = socfpga_cpu_standby,
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.pwr_domain_on = socfpga_pwr_domain_on,
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.pwr_domain_off = socfpga_pwr_domain_off,
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.pwr_domain_suspend = socfpga_pwr_domain_suspend,
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.pwr_domain_on_finish = socfpga_pwr_domain_on_finish,
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.pwr_domain_suspend_finish = socfpga_pwr_domain_suspend_finish,
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.system_off = socfpga_system_off,
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.system_reset = socfpga_system_reset,
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.system_reset2 = socfpga_system_reset2,
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.validate_power_state = socfpga_validate_power_state,
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.validate_ns_entrypoint = socfpga_validate_ns_entrypoint,
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.get_sys_suspend_power_state = socfpga_get_sys_suspend_power_state
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};
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/*******************************************************************************
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* Export the platform specific power ops.
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******************************************************************************/
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const struct plat_psci_ops **psci_ops)
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{
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/* Save warm boot entrypoint.*/
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mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint);
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*psci_ops = &socfpga_psci_pm_ops;
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return 0;
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}
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