mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
Merge changes Id85b2541,I4d253e2f into integration
* changes: fix(intel): update system counter back to 400MHz fix(intel): revert back to use L4 clock
This commit is contained in:
Sandrine Bailleux
TrustedFirmware Code Review
commit
9c653440f6
6 changed files with 60 additions and 47 deletions
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@ -9,6 +9,7 @@
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#define PLAT_SOCFPGA_DEF_H
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#include "agilex_system_manager.h"
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#include <lib/utils_def.h>
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#include <platform_def.h>
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/* Platform Setting */
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@ -90,8 +91,8 @@
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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/*******************************************************************************
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* SDMMC related pointer function
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@ -106,6 +107,6 @@
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#define L2_RESET_DONE_REG 0xFFD12218
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/* Platform specific system counter */
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
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#endif /* PLAT_SOCFPGA_DEF_H */
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@ -398,12 +398,21 @@ uint32_t get_mpu_clk(void)
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return mpu_clk;
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}
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uint32_t get_l4_clk(void)
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{
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uint32_t l4_clk;
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l4_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1,
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CLKMGR_PERPLL_PLLC1);
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return l4_clk;
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}
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/* Get cpu freq clock */
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uint32_t get_cpu_clk(void)
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{
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uint32_t cpu_clk;
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cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
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cpu_clk = get_l4_clk()/PLAT_HZ_CONVERT_TO_MHZ;
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return cpu_clk;
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}
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@ -9,14 +9,15 @@
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#define PLAT_SOCFPGA_DEF_H
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#include <platform_def.h>
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#include <lib/utils_def.h>
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#include "n5x_system_manager.h"
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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@ -34,10 +35,10 @@
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#define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000)
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#define SOCFPGA_ECC_QSPI_REG_BASE U(0xffa22000)
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#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
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#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
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#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
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#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
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#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
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#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
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#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
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#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
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/*******************************************************************************
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@ -64,17 +65,17 @@
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#define DEVICE4_BASE (0x2000000000)
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#define DEVICE4_SIZE (0x0100000000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe1b000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe1b000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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/*******************************************************************************
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* WDT related constants
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@ -84,19 +85,19 @@
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/*******************************************************************************
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* GIC related constants
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******************************************************************************/
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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/*******************************************************************************
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* SDMMC related pointer function
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******************************************************************************/
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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/*******************************************************************************
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* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
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@ -105,6 +106,6 @@
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#define L2_RESET_DONE_REG 0xFFD12218
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/* Platform specific system counter */
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
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#endif /* PLAT_SOCFPGA_DEF_H */
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@ -150,7 +150,7 @@ uint32_t get_cpu_clk(void)
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{
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uint32_t cpu_clk = 0;
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cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
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cpu_clk = get_l4_clk()/PLAT_HZ_CONVERT_TO_MHZ;
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return cpu_clk;
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}
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@ -95,6 +95,7 @@ uint32_t get_wdt_clk(void);
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uint32_t get_uart_clk(void);
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uint32_t get_mmc_clk(void);
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uint32_t get_l3_clk(uint32_t ref_clk);
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uint32_t get_cpu_clk(void);
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uint32_t get_ref_clk(uint32_t pllglob);
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uint32_t get_mpu_periph_clk(void);
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@ -8,14 +8,15 @@
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#define PLAT_SOCFPGA_DEF_H
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#include <platform_def.h>
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#include <lib/utils_def.h>
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#include "s10_system_manager.h"
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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@ -64,17 +65,17 @@
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#define DEVICE4_BASE (0x2000000000)
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#define DEVICE4_SIZE (0x0100000000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe2b000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe2b000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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/*******************************************************************************
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* WDT related constants
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@ -84,19 +85,19 @@
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/*******************************************************************************
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* GIC related constants
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******************************************************************************/
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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/*******************************************************************************
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* SDMMC related pointer function
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******************************************************************************/
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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/*******************************************************************************
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* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
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@ -105,7 +106,7 @@
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#define L2_RESET_DONE_REG 0xFFD12218
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/* Platform specific system counter */
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
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#endif /* PLATSOCFPGA_DEF_H */
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