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fix(intel): refactor SDMMC driver for Altera products

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Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2024-10-25 09:37:42 +08:00
parent 5d23325e6b
commit beba20403e
11 changed files with 752 additions and 1276 deletions
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987
drivers/cadence/emmc/cdns_sdmmc.c
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File diff suppressed because it is too large Load diff

323
include/drivers/cadence/cdns_sdmmc.h
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@ -1,6 +1,7 @@
/*
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,23 +11,26 @@
#include <drivers/cadence/cdns_combo_phy.h>
#include <drivers/mmc.h>
#include "socfpga_plat_def.h"
#if MMC_DEVICE_TYPE == 0
#define CONFIG_DMA_ADDR_T_64BIT 0
#define CONFIG_DMA_ADDR_T_64BIT 0
#endif
#define MMC_REG_BASE SOCFPGA_MMC_REG_BASE
#define COMBO_PHY_REG 0x0
#define SDHC_EXTENDED_WR_MODE_MASK 0xFFFFFFF7
#define SDHC_DLL_RESET_MASK 0x00000001
#define MMC_REG_BASE SOCFPGA_MMC_REG_BASE
#define COMBO_PHY_REG 0x0
#define SDHC_EXTENDED_WR_MODE_MASK 0xFFFFFFF7
#define SDHC_DLL_RESET_MASK 0x00000001
#define MMC_MAX_BLOCK_LEN 512U
/* HRS09 */
#define SDHC_PHY_SW_RESET BIT(0)
#define SDHC_PHY_INIT_COMPLETE BIT(1)
#define SDHC_EXTENDED_RD_MODE(x) ((x) << 2)
#define SDHC_PHY_INIT_COMPLETE BIT(1)
#define SDHC_EXTENDED_RD_MODE(x) ((x) << 2)
#define EXTENDED_WR_MODE 3
#define SDHC_EXTENDED_WR_MODE(x) ((x) << 3)
#define RDCMD_EN 15
#define SDHC_EXTENDED_WR_MODE(x) ((x) << 3)
#define RDCMD_EN (3 << 15)
#define PHY_SW_RESET_EN (1 << 0)
#define PHY_INIT_COMPLETE_BIT (1 << 1)
#define SDHC_RDCMD_EN(x) ((x) << 15)
#define SDHC_RDDATA_EN(x) ((x) << 16)
@ -38,9 +42,9 @@
/* • 1111b - Reserved */
/* • 1110b - t_sdmclk*2(27+2) */
/* • 1101b - t_sdmclk*2(26+2) */
#define READ_CLK 0xa << 16
#define WRITE_CLK 0xe << 16
#define DTC_VAL 0xE
#define READ_CLK 0xa << 16
#define WRITE_CLK 0xe << 16
#define DTC_VAL 0xE
/* SRS00 */
/* System Address / Argument 2 / 32-bit block count
@ -49,18 +53,18 @@
* • SDMA system memory address
* • Auto CMD23 Argument
*/
#define SAAR (1)
#define SAAR (1)
/* SRS01 */
/* Transfer Block Size
* This field defines block size for block data transfers
*/
#define BLOCK_SIZE 0
#define BLOCK_SIZE 0
/* SDMA Buffer Boundary
* System address boundary can be set for SDMA engine.
*/
#define SDMA_BUF 7 << 12
#define SDMA_BUF 7 << 12
/* Block Count For Current Transfer
* To set the number of data blocks can be defined for next transfer
@ -68,93 +72,108 @@
#define BLK_COUNT_CT 16
/* SRS03 */
#define CMD_START (U(1) << 31)
#define CMD_START (U(1) << 31)
#define CMD_USE_HOLD_REG (1 << 29)
#define CMD_UPDATE_CLK_ONLY (1 << 21)
#define CMD_SEND_INIT (1 << 15)
#define CMD_STOP_ABORT_CMD (4 << 22)
#define CMD_RESUME_CMD (2 << 22)
#define CMD_SUSPEND_CMD (1 << 22)
#define DATA_PRESENT (1 << 21)
#define CMD_IDX_CHK_ENABLE (1 << 20)
#define CMD_WRITE (0 << 4)
#define CMD_READ (1 << 4)
#define DATA_PRESENT (0x20)
#define CMD_IDX_CHK_ENABLE (0x10)
#define CMD_WRITE (0 << 4)
#define CMD_READ (1 << 4)
#define MULTI_BLK_READ (1 << 5)
#define RESP_ERR (1 << 7)
#define CMD_CHECK_RESP_CRC (1 << 19)
#define RES_TYPE_SEL_48 (2 << 16)
#define RES_TYPE_SEL_136 (1 << 16)
#define RES_TYPE_SEL_48_B (3 << 16)
#define RES_TYPE_SEL_NO (0 << 16)
#define DMA_ENABLED (1 << 0)
#define BLK_CNT_EN (1 << 1)
#define AUTO_CMD_EN (2 << 2)
#define COM_IDX 24
#define ERROR_INT (1 << 15)
#define INT_SBE (1 << 13)
#define INT_HLE (1 << 12)
#define INT_FRUN (1 << 11)
#define INT_DRT (1 << 9)
#define INT_RTO (1 << 8)
#define INT_DCRC (1 << 7)
#define INT_RCRC (1 << 6)
#define INT_RXDR (1 << 5)
#define INT_TXDR (1 << 4)
#define INT_DTO (1 << 3)
#define RESP_ERR (1 << 7)
#define CMD_CHECK_RESP_CRC (0x08)
#define RES_TYPE_SEL_48 (0x2)
#define RES_TYPE_SEL_136 (0x1)
#define RES_TYPE_SEL_48_B (0x3)
#define RES_TYPE_SEL_NO (0x3)
#define DMA_ENABLED (1 << 0)
#define BLK_CNT_EN (1 << 1)
#define AUTO_CMD_EN (2 << 2)
#define COM_IDX 24
#define ERROR_INT (1 << 15)
#define INT_SBE (1 << 13)
#define INT_HLE (1 << 12)
#define INT_FRUN (1 << 11)
#define INT_DRT (1 << 9)
#define INT_RTO (1 << 8)
#define INT_DCRC (1 << 7)
#define INT_RCRC (1 << 6)
#define INT_RXDR (1 << 5)
#define INT_TXDR (1 << 4)
#define INT_DTO (1 << 3)
#define INT_CMD_DONE (1 << 0)
#define TRAN_COMP (1 << 1)
#define TRAN_COMP (1 << 1)
/* SRS09 */
#define STATUS_DATA_BUSY BIT(2)
#define CI 16
#define CHECK_CARD BIT(CI)
/* SRS10 */
#define BIT1 (0 << 1)
#define BIT4 (1 << 1)
#define BIT8 (1 << 5)
/* LED Control
* State of this bit directly drives led port of the host
* in order to control the external LED diode
* Default value 0 << 1
*/
#define LEDC BIT(0)
#define LEDC_OFF 0 << 1
#define LEDC BIT(0)
#define LEDC_OFF (0 << 1)
/* Data Transfer Width
* Bit used to configure DAT bus width to 1 or 4
* Default value 1 << 1
*/
#define DT_WIDTH BIT(1)
#define DTW_4BIT 1 << 1
#define DT_WIDTH BIT(1)
#define DTW_4BIT (1 << 1)
/* Extended Data Transfer Width
* This bit is to enable/disable 8-bit DAT bus width mode
* Default value 1 << 5
*/
#define EDTW_8BIT 1 << 5
#define EDTW_8BIT BIT(5)
/* High Speed Enable
* Selects operating mode to Default Speed (HSE=0) or High Speed (HSE=1)
*/
#define HS_EN BIT(2)
#define HS_EN BIT(2)
/* here 0 defines the 64 Kb size */
#define MAX_64KB_PAGE 0
#define EMMC_DESC_SIZE (1<<20)
#define EMMC_DESC_SIZE (1<<20)
#define DTCV_OFFSET (0x22E)
#define DTCV_VAL (0xE)
#define CICE_OFFSET (0x20E)
#define SRS_12_CC_EN (1 << 0)
/* SRS11 */
/* Software Reset For All
* When set to 1, the entire slot is reset
* After completing the reset operation, SRFA bit is automatically cleared
*/
#define SRFA BIT(24)
#define SRFA BIT(24)
/* Software Reset For CMD Line
* When set to 1, resets the logic related to the command generation and response checking
*/
#define SRCMD BIT(25)
#define SRCMD BIT(25)
/* Software Reset For DAT Line
* When set to 1, resets the logic related to the data path,
* including data buffers and the DMA logic
*/
#define SRDAT BIT(26)
#define SRDAT BIT(26)
/* SRS12 */
/* Error mask */
#define SRS12_ERR_MASK 0xFFFF8000U
#define CDNS_CSD_BYTE_MASK 0x000000FFU
/* SRS15 */
/* UHS Mode Select
@ -165,40 +184,43 @@
* • 011b - SDR104
* • 100b - DDR50
*/
#define SDR12_MODE 0 << 16
#define SDR25_MODE 1 << 16
#define SDR50_MODE 2 << 16
#define SDR104_MODE 3 << 16
#define DDR50_MODE 4 << 16
#define SDR12_MODE 0 << 16
#define SDR25_MODE 1 << 16
#define SDR50_MODE 2 << 16
#define SDR104_MODE 3 << 16
#define DDR50_MODE 4 << 16
/* 1.8V Signaling Enable
* • 0 - for Default Speed, High Speed mode
* • 1 - for UHS-I mode
*/
#define V18SE BIT(19)
#define V18SE BIT(19)
/* CMD23 Enable
* In result of Card Identification process,
* Host Driver set this bit to 1 if Card supports CMD23
*/
#define CMD23_EN BIT(27)
#define CMD23_EN BIT(27)
/* Host Version 4.00 Enable
* • 0 - Version 3.00
* • 1 - Version 4.00
*/
#define HV4E BIT(28)
#define HV4E BIT(28)
/* Conf depends on SRS15.HV4E */
#define SDMA 0 << 3
#define ADMA2_32 2 << 3
#define ADMA2_64 3 << 3
#define SDMA 0 << 3
#define ADMA2_32 2 << 3
#define ADMA2_64 3 << 3
#define DMA_SEL_BIT 3 << 3
#define DMA_SEL_BIT_2 2 << 3
#define DMA_SEL_BIT_3 3 << 3
/* Preset Value Enable
* Setting this bit to 1 triggers an automatically update of SRS11
*/
#define PVE BIT(31)
#define PVE BIT(31)
#define BIT_AD_32 0 << 29
#define BIT_AD_64 1 << 29
#define BIT_AD_32 0 << 29
#define BIT_AD_64 1 << 29
/* SW RESET REG*/
#define SDHC_CDNS_HRS00 (0x00)
@ -206,7 +228,7 @@
/* PHY access port */
#define SDHC_CDNS_HRS04 0x10
#define SDHC_CDNS_HRS04_ADDR GENMASK(5, 0)
#define SDHC_CDNS_HRS04_ADDR GENMASK(5, 0)
/* PHY data access port */
#define SDHC_CDNS_HRS05 0x14
@ -233,14 +255,51 @@
#define SDHC_CDNS_SRS13 0x234
#define SDHC_CDNS_SRS14 0x238
#define SDHC_CDNS_SRS15 0x23c
#define SDHC_CDNS_SRS16 0x240
#define SDHC_CDNS_SRS21 0x254
#define SDHC_CDNS_SRS22 0x258
#define SDHC_CDNS_SRS23 0x25c
#define SDHC_CDNS_SRS24 0x260
#define SDHC_CDNS_SRS25 0x264
/* SRS00 */
#define SAAR (1)
/* SRS03 */
#define CMD_START (U(1) << 31)
#define CMD_USE_HOLD_REG (1 << 29)
#define CMD_UPDATE_CLK_ONLY (1 << 21)
#define CMD_SEND_INIT (1 << 15)
#define CMD_STOP_ABORT_CMD (4 << 22)
#define CMD_RESUME_CMD (2 << 22)
#define CMD_SUSPEND_CMD (1 << 22)
#define DMA_ENABLED (1 << 0)
#define BLK_CNT_EN (1 << 1)
#define AUTO_CMD_EN (2 << 2)
#define COM_IDX 24
#define ERROR_INT (1 << 15)
#define INT_SBE (1 << 13)
#define INT_HLE (1 << 12)
#define INT_FRUN (1 << 11)
#define INT_DRT (1 << 9)
#define INT_RTO (1 << 8)
#define INT_DCRC (1 << 7)
#define INT_RCRC (1 << 6)
#define INT_RXDR (1 << 5)
#define INT_TXDR (1 << 4)
#define INT_DTO (1 << 3)
#define INT_CMD_DONE (1 << 0)
#define TRAN_COMP (1 << 1)
#define CDNS_HOST_CMD_INHIBIT (BIT(0))
#define CDNS_HOST_DATA_INHIBIT (BIT(1))
#define ACE_CMD_12 (BIT(2))
#define PAGE_BUFFER_LEN (64 * 1024)
/* HRS07 */
#define SDHC_CDNS_HRS07 0x1c
#define SDHC_IDELAY_VAL(x) ((x) << 0)
#define SDHC_RW_COMPENSATE(x) ((x) << 16)
#define SDHC_RW_COMPENSATE(x) ((x) << 16)
/* PHY reset port */
#define SDHC_CDNS_HRS09 0x24
@ -254,49 +313,49 @@
/* Pinmux headers will reomove after ATF driver implementation */
#define PINMUX_SDMMC_SEL 0x0
#define PIN0SEL 0x00
#define PIN1SEL 0x04
#define PIN2SEL 0x08
#define PIN3SEL 0x0C
#define PIN4SEL 0x10
#define PIN5SEL 0x14
#define PIN6SEL 0x18
#define PIN7SEL 0x1C
#define PIN8SEL 0x20
#define PIN9SEL 0x24
#define PIN10SEL 0x28
#define PIN0SEL 0x00
#define PIN1SEL 0x04
#define PIN2SEL 0x08
#define PIN3SEL 0x0C
#define PIN4SEL 0x10
#define PIN5SEL 0x14
#define PIN6SEL 0x18
#define PIN7SEL 0x1C
#define PIN8SEL 0x20
#define PIN9SEL 0x24
#define PIN10SEL 0x28
/* HRS16 */
#define SDHC_WRCMD0_DLY(x) ((x) << 0)
#define SDHC_WRCMD1_DLY(x) ((x) << 4)
#define SDHC_WRDATA0_DLY(x) ((x) << 8)
#define SDHC_WRDATA1_DLY(x) ((x) << 12)
#define SDHC_WRCMD0_SDCLK_DLY(x) ((x) << 16)
#define SDHC_WRCMD1_SDCLK_DLY(x) ((x) << 20)
#define SDHC_WRDATA0_SDCLK_DLY(x) ((x) << 24)
#define SDHC_WRDATA1_SDCLK_DLY(x) ((x) << 28)
#define SDHC_WRCMD0_SDCLK_DLY(x) ((x) << 16)
#define SDHC_WRCMD1_SDCLK_DLY(x) ((x) << 20)
#define SDHC_WRDATA0_SDCLK_DLY(x) ((x) << 24)
#define SDHC_WRDATA1_SDCLK_DLY(x) ((x) << 28)
/* Shared Macros */
#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \
(SDMMC_CDN_##_reg))
/* MMC Peripheral Definition */
#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000)
#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000)
#define MMC_RESPONSE_NONE 0
#define SDHC_CDNS_SRS03_VALUE 0x01020013
#define SDHC_CDNS_SRS03_VALUE 0x01020013
/* Value randomly chosen for eMMC RCA, it should be > 1 */
#define MMC_FIX_RCA 6
#define MMC_FIX_RCA 6
#define RCA_SHIFT_OFFSET 16
#define CMD_EXTCSD_PARTITION_CONFIG 179
#define CMD_EXTCSD_BUS_WIDTH 183
#define CMD_EXTCSD_HS_TIMING 185
#define CMD_EXTCSD_PARTITION_CONFIG 179
#define CMD_EXTCSD_BUS_WIDTH 183
#define CMD_EXTCSD_HS_TIMING 185
#define CMD_EXTCSD_SEC_CNT 212
#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
#define PART_CFG_PARTITION1_ACCESS (U(1) << 0)
#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
#define PART_CFG_PARTITION1_ACCESS (U(1) << 0)
/* Values in EXT CSD register */
#define MMC_BUS_WIDTH_1 U(0)
@ -304,8 +363,8 @@
#define MMC_BUS_WIDTH_8 U(2)
#define MMC_BUS_WIDTH_DDR_4 U(5)
#define MMC_BUS_WIDTH_DDR_8 U(6)
#define MMC_BOOT_MODE_BACKWARD (U(0) << 3)
#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3)
#define MMC_BOOT_MODE_BACKWARD (U(0) << 3)
#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3)
#define MMC_BOOT_MODE_DDR (U(2) << 3)
#define EXTCSD_SET_CMD (U(0) << 24)
@ -314,14 +373,14 @@
#define EXTCSD_WRITE_BYTES (U(3) << 24)
#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
#define EXTCSD_CMD_SET_NORMAL U(1)
#define EXTCSD_CMD_SET_NORMAL U(1)
#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
#define CSD_TRAN_SPEED_MULT_SHIFT 3
#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
#define CSD_TRAN_SPEED_MULT_SHIFT 3
#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
#define STATUS_READY_FOR_DATA BIT(8)
#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
#define STATUS_READY_FOR_DATA BIT(8)
#define STATUS_SWITCH_ERROR BIT(7)
#define MMC_GET_STATE(x) (((x) >> 9) & 0xf)
#define MMC_STATE_IDLE 0
@ -342,12 +401,51 @@
#define VHS_2_7_3_6_V BIT(8)
/*ADMA table component*/
#define ADMA_DESC_ATTR_VALID BIT(0)
#define ADMA_DESC_ATTR_VALID BIT(0)
#define ADMA_DESC_ATTR_END BIT(1)
#define ADMA_DESC_ATTR_INT BIT(2)
#define ADMA_DESC_ATTR_ACT1 BIT(4)
#define ADMA_DESC_ATTR_ACT2 BIT(5)
#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
#define HRS_09_EXTENDED_RD_MODE (1 << 2)
#define HRS_09_EXTENDED_WR_MODE (1 << 3)
#define HRS_09_RDCMD_EN (1 << 15)
#define HRS_09_RDDATA_EN (1 << 16)
#define HRS_10_HCSDCLKADJ_VAL (3)
#define SRS11_SRFA (1 << 24)
#define SRS11_SRFA_CHK(x) (x >> 24)
#define CDNS_TIMEOUT (5000)
#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
/* Card busy and present */
#define CARD_BUSY 1
#define CARD_NOT_BUSY 0
/* 500 ms delay to read the RINST register */
#define DELAY_MS_SRS_READ 500
#define DELAY_RES 10
/* Check DV dfi_init val=0 */
#define IO_MASK_END_DATA 0x0
/* Check DV dfi_init val=2; DDR Mode */
#define IO_MASK_END_DATA_DDR 0x2
#define IO_MASK_START_DATA 0x0
#define DATA_SELECT_OE_END_DATA 0x1
#define TIMEOUT 100000
/* General define */
#define SDHC_REG_MASK UINT_MAX
#define SD_HOST_BLOCK_SIZE 0x200
#define DTCVVAL_DEFAULT_VAL 0xE
#define CDMMC_DMA_MAX_BUFFER_SIZE 64*1024
#define CDNSMMC_ADDRESS_MASK U(0x0f)
#define CONFIG_CDNS_DESC_COUNT 8
#define SD_HOST_CLK 200000000
enum sd_opcode {
SD_GO_IDLE_STATE = 0,
@ -388,6 +486,16 @@ enum sd_app_cmd {
SD_APP_SEND_SCR = 51,
};
enum sd_opr_modes {
SD_HOST_OPR_MODE_HV4E_0_SDMA_32 = 0,
SD_HOST_OPR_MODE_HV4E_1_SDMA_32,
SD_HOST_OPR_MODE_HV4E_1_SDMA_64,
SD_HOST_OPR_MODE_HV4E_0_ADMA_32,
SD_HOST_OPR_MODE_HV4E_0_ADMA_64,
SD_HOST_OPR_MODE_HV4E_1_ADMA_32,
SD_HOST_OPR_MODE_HV4E_1_ADMA_64,
};
struct cdns_sdmmc_sdhc {
uint32_t sdhc_extended_rd_mode;
uint32_t sdhc_extended_wr_mode;
@ -439,9 +547,6 @@ struct cdns_sdmmc_params {
uint32_t combophy;
};
/* read and write API */
size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size);
size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size);
struct cdns_idmac_desc {
/*8 bit attribute*/
@ -467,4 +572,8 @@ int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg,
struct cdns_sdmmc_sdhc *mmc_sdhc_reg);
void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg,
struct cdns_sdmmc_sdhc *sdhc_reg);
int cdns_mmc_init(struct cdns_sdmmc_params *params, struct mmc_device_info *info);
int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg,
struct cdns_sdmmc_sdhc *sdhc_reg);
void cdns_host_set_clk(uint32_t clk);
#endif

20
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -35,12 +35,24 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
/* FIP Setting */
#define PLAT_FIP_BASE (0)
#if ARM_LINUX_KERNEL_AS_BL33
#define PLAT_FIP_MAX_SIZE (0x8000000)
#else
#define PLAT_FIP_MAX_SIZE (0x1000000)
#endif
/* SDMMC Setting */
# if ARM_LINUX_KERNEL_AS_BL33
#if ARM_LINUX_KERNEL_AS_BL33
#define PLAT_MMC_DATA_BASE (0x10000000)
#define PLAT_MMC_DATA_SIZE (0x100000)
#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
# else
#else
#define PLAT_MMC_DATA_BASE (0xffe3c000)
#define PLAT_MMC_DATA_SIZE (0x2000
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
# endif
#endif
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
@ -112,7 +124,7 @@
/*******************************************************************************
* SDMMC related pointer function
******************************************************************************/
#define SDMMC_READ_BLOCKS mmc_read_blocks
#define SDMMC_READ_BLOCKS sdmmc_read_blocks
#define SDMMC_WRITE_BLOCKS mmc_write_blocks
/*******************************************************************************

1
plat/intel/soc/agilex/platform.mk
View file

@ -28,6 +28,7 @@ PLAT_BL_COMMON_SOURCES := \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S \
plat/intel/soc/common/drivers/ccu/ncore_ccu.c \
plat/intel/soc/common/drivers/sdmmc/sdmmc.c \
plat/intel/soc/common/lib/sha/sha.c \
plat/intel/soc/common/socfpga_delay_timer.c

11
plat/intel/soc/agilex5/bl2_plat_setup.c
View file

@ -103,6 +103,15 @@ void bl2_el3_early_platform_setup(u_register_t x0 __unused,
/* Configure the pinmux */
config_pinmux(&reverse_handoff_ptr);
/* Configure OCRAM to NON SECURE ACCESS */
mmio_write_32(OCRAM_REGION_0_REG_BASE, OCRAM_NON_SECURE_ENABLE);
mmio_write_32(SOCFPGA_L4_PER_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
SOCFPGA_SDMMC_SECU_BIT_ENABLE);
mmio_write_32(SOCFPGA_L4_SYS_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
SOCFPGA_SDMMC_SECU_BIT_ENABLE);
mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE,
SOCFPGA_LWSOC2FPGA_ENABLE);
/* Configure the clock manager */
if ((config_clkmgr_handoff(&reverse_handoff_ptr)) != 0) {
ERROR("SOCFPGA: Failed to initialize the clock manager\n");
@ -156,7 +165,7 @@ void bl2_el3_plat_arch_setup(void)
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
NOTICE("SDMMC boot\n");
sdmmc_init(&reverse_handoff_ptr, &params, &mmc_info);
cdns_mmc_init(&params, &mmc_info);
socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
break;

30
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -46,12 +46,24 @@
#define CAD_QSPIDATA_OFST 0x10900000
#define CAD_QSPI_OFFSET 0x108d2000
/* FIP Setting */
#define PLAT_FIP_BASE (0)
#if ARM_LINUX_KERNEL_AS_BL33
#define PLAT_FIP_MAX_SIZE (0x8000000)
#else
#define PLAT_FIP_MAX_SIZE (0x1000000)
#endif
/* SDMMC Setting */
# if ARM_LINUX_KERNEL_AS_BL33
#if ARM_LINUX_KERNEL_AS_BL33
#define PLAT_MMC_DATA_BASE (0x90000000)
#define PLAT_MMC_DATA_SIZE (0x100000)
#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
# else
#else
#define PLAT_MMC_DATA_BASE (0x0007D000)
#define PLAT_MMC_DATA_SIZE (0x2000)
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
# endif
#endif
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000
@ -69,10 +81,22 @@
#define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100
#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200
#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300
#define SOCFPGA_SDMMC_SECU_BIT 0x40
#define SOCFPGA_LWSOC2FPGA_ENABLE 0xffe0301
#define SOCFPGA_SDMMC_SECU_BIT_ENABLE 0x1010001
/* Define maximum page size for NAND flash devices */
#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000)
/* OCRAM Register*/
#define OCRAM_REG_BASE 0x108CC400
#define OCRAM_REGION_0_OFFSET 0x18
#define OCRAM_REGION_0_REG_BASE (OCRAM_REG_BASE + \
OCRAM_REGION_0_OFFSET)
#define OCRAM_NON_SECURE_ENABLE 0x0
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/

611
plat/intel/soc/common/drivers/sdmmc/sdmmc.c
View file

@ -18,53 +18,26 @@
#include <lib/mmio.h>
#include <lib/utils.h>
#include "agilex5_pinmux.h"
#include "sdmmc.h"
#include "socfpga_mailbox.h"
#include "wdt/watchdog.h"
static const struct mmc_ops *ops;
static unsigned int mmc_ocr_value;
static struct mmc_csd_emmc mmc_csd;
static struct sd_switch_status sd_switch_func_status;
static unsigned char mmc_ext_csd[512] __aligned(16);
static unsigned int mmc_flags;
static struct mmc_device_info *mmc_dev_info;
static unsigned int rca;
static unsigned int scr[2]__aligned(16) = { 0 };
extern const struct mmc_ops cdns_sdmmc_ops;
extern struct cdns_sdmmc_params cdns_params;
extern struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg;
extern struct cdns_sdmmc_sdhc sdmmc_sdhc_reg;
static bool is_cmd23_enabled(void)
bool is_cmd23_enabled(void)
{
return ((mmc_flags & MMC_FLAG_CMD23) != 0U);
}
static bool is_sd_cmd6_enabled(void)
{
return ((mmc_flags & MMC_FLAG_SD_CMD6) != 0U);
}
/* TODO: Will romove once ATF driver is developed */
void sdmmc_pin_config(void)
{
/* temp use base + addr. Official must change to common method */
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x00, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x04, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x08, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x0C, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x10, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x14, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x18, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x1C, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x20, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x24, 0x0);
mmio_write_32(AGX5_PINMUX_PIN0SEL+0x28, 0x0);
}
static int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
unsigned int r_type, unsigned int *r_data)
{
struct mmc_cmd cmd;
@ -94,7 +67,7 @@ static int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
return ret;
}
static int sdmmc_device_state(void)
int sdmmc_device_state(void)
{
int retries = DEFAULT_SDMMC_MAX_RETRIES;
unsigned int resp_data[4];
@ -125,521 +98,12 @@ static int sdmmc_device_state(void)
return MMC_GET_STATE(resp_data[0]);
}
static int sdmmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
{
int ret;
ret = sdmmc_send_cmd(MMC_CMD(6),
EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
EXTCSD_VALUE(value) | EXTCSD_CMD_SET_NORMAL,
MMC_RESPONSE_R1B, NULL);
if (ret != 0) {
return ret;
}
do {
ret = sdmmc_device_state();
if (ret < 0) {
return ret;
}
} while (ret == MMC_STATE_PRG);
return 0;
}
static int sdmmc_mmc_sd_switch(unsigned int bus_width)
{
int ret;
int retries = DEFAULT_SDMMC_MAX_RETRIES;
unsigned int bus_width_arg = 0;
/* CMD55: Application Specific Command */
ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET,
MMC_RESPONSE_R5, NULL);
if (ret != 0) {
return ret;
}
ret = ops->prepare(0, (uintptr_t)&scr, sizeof(scr));
if (ret != 0) {
return ret;
}
/* ACMD51: SEND_SCR */
do {
ret = sdmmc_send_cmd(MMC_ACMD(51), 0, MMC_RESPONSE_R1, NULL);
if ((ret != 0) && (retries == 0)) {
ERROR("ACMD51 failed after %d retries (ret=%d)\n",
DEFAULT_SDMMC_MAX_RETRIES, ret);
return ret;
}
retries--;
} while (ret != 0);
ret = ops->read(0, (uintptr_t)&scr, sizeof(scr));
if (ret != 0) {
return ret;
}
if (((scr[0] & SD_SCR_BUS_WIDTH_4) != 0U) &&
(bus_width == MMC_BUS_WIDTH_4)) {
bus_width_arg = 2;
}
/* CMD55: Application Specific Command */
ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET,
MMC_RESPONSE_R5, NULL);
if (ret != 0) {
return ret;
}
/* ACMD6: SET_BUS_WIDTH */
ret = sdmmc_send_cmd(MMC_ACMD(6), bus_width_arg, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
do {
ret = sdmmc_device_state();
if (ret < 0) {
return ret;
}
} while (ret == MMC_STATE_PRG);
return 0;
}
static int sdmmc_set_ios(unsigned int clk, unsigned int bus_width)
{
int ret;
unsigned int width = bus_width;
if (mmc_dev_info->mmc_dev_type != MMC_IS_EMMC) {
if (width == MMC_BUS_WIDTH_8) {
WARN("Wrong bus config for SD-card, force to 4\n");
width = MMC_BUS_WIDTH_4;
}
ret = sdmmc_mmc_sd_switch(width);
if (ret != 0) {
return ret;
}
} else if (mmc_csd.spec_vers == 4U) {
ret = sdmmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH,
(unsigned int)width);
if (ret != 0) {
return ret;
}
} else {
VERBOSE("Wrong MMC type or spec version\n");
}
return ops->set_ios(clk, width);
}
static int sdmmc_fill_device_info(void)
{
unsigned long long c_size;
unsigned int speed_idx;
unsigned int nb_blocks;
unsigned int freq_unit;
int ret = 0;
struct mmc_csd_sd_v2 *csd_sd_v2;
switch (mmc_dev_info->mmc_dev_type) {
case MMC_IS_EMMC:
mmc_dev_info->block_size = MMC_BLOCK_SIZE;
ret = ops->prepare(0, (uintptr_t)&mmc_ext_csd,
sizeof(mmc_ext_csd));
if (ret != 0) {
return ret;
}
/* MMC CMD8: SEND_EXT_CSD */
ret = sdmmc_send_cmd(MMC_CMD(8), 0, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
ret = ops->read(0, (uintptr_t)&mmc_ext_csd,
sizeof(mmc_ext_csd));
if (ret != 0) {
return ret;
}
do {
ret = sdmmc_device_state();
if (ret < 0) {
return ret;
}
} while (ret != MMC_STATE_TRAN);
nb_blocks = (mmc_ext_csd[CMD_EXTCSD_SEC_CNT] << 0) |
(mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 1] << 8) |
(mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 2] << 16) |
(mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 3] << 24);
mmc_dev_info->device_size = (unsigned long long)nb_blocks *
mmc_dev_info->block_size;
break;
case MMC_IS_SD:
/*
* Use the same mmc_csd struct, as required fields here
* (READ_BL_LEN, C_SIZE, CSIZE_MULT) are common with eMMC.
*/
mmc_dev_info->block_size = BIT_32(mmc_csd.read_bl_len);
c_size = ((unsigned long long)mmc_csd.c_size_high << 2U) |
(unsigned long long)mmc_csd.c_size_low;
assert(c_size != 0xFFFU);
mmc_dev_info->device_size = (c_size + 1U) *
BIT_64(mmc_csd.c_size_mult + 2U) *
mmc_dev_info->block_size;
break;
case MMC_IS_SD_HC:
assert(mmc_csd.csd_structure == 1U);
mmc_dev_info->block_size = MMC_BLOCK_SIZE;
/* Need to use mmc_csd_sd_v2 struct */
csd_sd_v2 = (struct mmc_csd_sd_v2 *)&mmc_csd;
c_size = ((unsigned long long)csd_sd_v2->c_size_high << 16) |
(unsigned long long)csd_sd_v2->c_size_low;
mmc_dev_info->device_size = (c_size + 1U) << SDMMC_MULT_BY_512K_SHIFT;
break;
default:
ret = -EINVAL;
break;
}
if (ret < 0) {
return ret;
}
speed_idx = (mmc_csd.tran_speed & CSD_TRAN_SPEED_MULT_MASK) >>
CSD_TRAN_SPEED_MULT_SHIFT;
assert(speed_idx > 0U);
if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
mmc_dev_info->max_bus_freq = tran_speed_base[speed_idx];
} else {
mmc_dev_info->max_bus_freq = sd_tran_speed_base[speed_idx];
}
freq_unit = mmc_csd.tran_speed & CSD_TRAN_SPEED_UNIT_MASK;
while (freq_unit != 0U) {
mmc_dev_info->max_bus_freq *= 10U;
--freq_unit;
}
mmc_dev_info->max_bus_freq *= 10000U;
return 0;
}
static int sdmmc_sd_switch(unsigned int mode, unsigned char group,
unsigned char func)
{
unsigned int group_shift = (group - 1U) * 4U;
unsigned int group_mask = GENMASK(group_shift + 3U, group_shift);
unsigned int arg;
int ret;
ret = ops->prepare(0, (uintptr_t)&sd_switch_func_status,
sizeof(sd_switch_func_status));
if (ret != 0) {
return ret;
}
/* MMC CMD6: SWITCH_FUNC */
arg = mode | SD_SWITCH_ALL_GROUPS_MASK;
arg &= ~group_mask;
arg |= func << group_shift;
ret = sdmmc_send_cmd(MMC_CMD(6), arg, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
return ops->read(0, (uintptr_t)&sd_switch_func_status,
sizeof(sd_switch_func_status));
}
static int sdmmc_sd_send_op_cond(void)
{
int n;
unsigned int resp_data[4];
for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) {
int ret;
/* CMD55: Application Specific Command */
ret = sdmmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
/* ACMD41: SD_SEND_OP_COND */
ret = sdmmc_send_cmd(MMC_ACMD(41), OCR_HCS |
mmc_dev_info->ocr_voltage, MMC_RESPONSE_R3,
&resp_data[0]);
if (ret != 0) {
return ret;
}
if ((resp_data[0] & OCR_POWERUP) != 0U) {
mmc_ocr_value = resp_data[0];
if ((mmc_ocr_value & OCR_HCS) != 0U) {
mmc_dev_info->mmc_dev_type = MMC_IS_SD_HC;
} else {
mmc_dev_info->mmc_dev_type = MMC_IS_SD;
}
return 0;
}
mdelay(10);
}
ERROR("ACMD41 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES);
return -EIO;
}
static int sdmmc_reset_to_idle(void)
{
int ret;
/* CMD0: reset to IDLE */
ret = sdmmc_send_cmd(MMC_CMD(0), 0, 0, NULL);
if (ret != 0) {
return ret;
}
mdelay(2);
return 0;
}
static int sdmmc_send_op_cond(void)
{
int ret, n;
unsigned int resp_data[4];
ret = sdmmc_reset_to_idle();
if (ret != 0) {
return ret;
}
for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) {
ret = sdmmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7,
MMC_RESPONSE_R3, &resp_data[0]);
if (ret != 0) {
return ret;
}
if ((resp_data[0] & OCR_POWERUP) != 0U) {
mmc_ocr_value = resp_data[0];
return 0;
}
mdelay(10);
}
ERROR("CMD1 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES);
return -EIO;
}
static int sdmmc_enumerate(unsigned int clk, unsigned int bus_width)
{
int ret;
unsigned int resp_data[4];
ops->init();
ret = sdmmc_reset_to_idle();
if (ret != 0) {
return ret;
}
if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
ret = sdmmc_send_op_cond();
} else {
/* CMD8: Send Interface Condition Command */
ret = sdmmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN,
MMC_RESPONSE_R5, &resp_data[0]);
if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) {
ret = sdmmc_sd_send_op_cond();
}
}
if (ret != 0) {
return ret;
}
/* CMD2: Card Identification */
ret = sdmmc_send_cmd(MMC_CMD(2), 0, MMC_RESPONSE_R2, NULL);
if (ret != 0) {
return ret;
}
/* CMD3: Set Relative Address */
if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
rca = MMC_FIX_RCA;
ret = sdmmc_send_cmd(MMC_CMD(3), rca << RCA_SHIFT_OFFSET,
MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
} else {
ret = sdmmc_send_cmd(MMC_CMD(3), 0,
MMC_RESPONSE_R6, &resp_data[0]);
if (ret != 0) {
return ret;
}
rca = (resp_data[0] & 0xFFFF0000U) >> 16;
}
/* CMD9: CSD Register */
ret = sdmmc_send_cmd(MMC_CMD(9), rca << RCA_SHIFT_OFFSET,
MMC_RESPONSE_R2, &resp_data[0]);
if (ret != 0) {
return ret;
}
memcpy_s(&mmc_csd, sizeof(mmc_csd) / MBOX_WORD_BYTE,
&resp_data, sizeof(resp_data) / MBOX_WORD_BYTE);
/* CMD7: Select Card */
ret = sdmmc_send_cmd(MMC_CMD(7), rca << RCA_SHIFT_OFFSET,
MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
do {
ret = sdmmc_device_state();
if (ret < 0) {
return ret;
}
} while (ret != MMC_STATE_TRAN);
ret = sdmmc_set_ios(clk, bus_width);
if (ret != 0) {
return ret;
}
ret = sdmmc_fill_device_info();
if (ret != 0) {
return ret;
}
if (is_sd_cmd6_enabled() &&
(mmc_dev_info->mmc_dev_type == MMC_IS_SD_HC)) {
/* Try to switch to High Speed Mode */
ret = sdmmc_sd_switch(SD_SWITCH_FUNC_CHECK, 1U, 1U);
if (ret != 0) {
return ret;
}
if ((sd_switch_func_status.support_g1 & BIT(9)) == 0U) {
/* High speed not supported, keep default speed */
return 0;
}
ret = sdmmc_sd_switch(SD_SWITCH_FUNC_SWITCH, 1U, 1U);
if (ret != 0) {
return ret;
}
if ((sd_switch_func_status.sel_g2_g1 & 0x1U) == 0U) {
/* Cannot switch to high speed, keep default speed */
return 0;
}
mmc_dev_info->max_bus_freq = 50000000U;
ret = ops->set_ios(clk, bus_width);
}
return ret;
}
size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size)
{
int ret;
unsigned int cmd_idx, cmd_arg;
mmc_read_blocks(lba, buf, size);
assert((ops != NULL) &&
(ops->read != NULL) &&
(size != 0U) &&
((size & MMC_BLOCK_MASK) == 0U));
ret = ops->prepare(lba, buf, size);
if (ret != 0) {
return 0;
}
if (is_cmd23_enabled()) {
/* Set block count */
ret = sdmmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE,
MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return 0;
}
cmd_idx = MMC_CMD(18);
} else {
if (size > MMC_BLOCK_SIZE) {
cmd_idx = MMC_CMD(18);
} else {
cmd_idx = MMC_CMD(17);
}
}
if (((mmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) &&
(mmc_dev_info->mmc_dev_type != MMC_IS_SD_HC)) {
cmd_arg = lba * MMC_BLOCK_SIZE;
} else {
cmd_arg = lba;
}
ret = sdmmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return 0;
}
ret = ops->read(lba, buf, size);
if (ret != 0) {
return 0;
}
/* Wait buffer empty */
do {
ret = sdmmc_device_state();
if (ret < 0) {
return 0;
}
} while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_DATA));
if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) {
ret = sdmmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL);
if (ret != 0) {
return 0;
}
}
/* Restart watchdog for reading each chunk byte */
watchdog_sw_rst();
return size;
}
@ -710,64 +174,3 @@ size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size)
return size;
}
int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
unsigned int width, unsigned int flags,
struct mmc_device_info *device_info)
{
assert((ops_ptr != NULL) &&
(ops_ptr->init != NULL) &&
(ops_ptr->send_cmd != NULL) &&
(ops_ptr->set_ios != NULL) &&
(ops_ptr->prepare != NULL) &&
(ops_ptr->read != NULL) &&
(ops_ptr->write != NULL) &&
(device_info != NULL) &&
(clk != 0) &&
((width == MMC_BUS_WIDTH_1) ||
(width == MMC_BUS_WIDTH_4) ||
(width == MMC_BUS_WIDTH_8) ||
(width == MMC_BUS_WIDTH_DDR_4) ||
(width == MMC_BUS_WIDTH_DDR_8)));
ops = ops_ptr;
mmc_flags = flags;
mmc_dev_info = device_info;
return sdmmc_enumerate(clk, width);
}
int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params, struct mmc_device_info *info)
{
int result = 0;
/* SDMMC pin mux configuration */
sdmmc_pin_config();
cdns_set_sdmmc_var(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
result = cdns_sd_host_init(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
if (result < 0) {
return result;
}
assert((params != NULL) &&
((params->reg_base & MMC_BLOCK_MASK) == 0) &&
((params->desc_base & MMC_BLOCK_MASK) == 0) &&
((params->desc_size & MMC_BLOCK_MASK) == 0) &&
((params->reg_pinmux & MMC_BLOCK_MASK) == 0) &&
((params->reg_phy & MMC_BLOCK_MASK) == 0) &&
(params->desc_size > 0) &&
(params->clk_rate > 0) &&
((params->bus_width == MMC_BUS_WIDTH_1) ||
(params->bus_width == MMC_BUS_WIDTH_4) ||
(params->bus_width == MMC_BUS_WIDTH_8)));
memcpy_s(&cdns_params, sizeof(struct cdns_sdmmc_params) / MBOX_WORD_BYTE,
params, sizeof(struct cdns_sdmmc_params) / MBOX_WORD_BYTE);
cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type;
cdns_params.cdn_sdmmc_dev_mode = SD_DS;
result = sd_or_mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width,
params->flags, info);
return result;
}

13
plat/intel/soc/common/drivers/sdmmc/sdmmc.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -33,10 +34,12 @@ static const unsigned char sd_tran_speed_base[16] = {
* @hoff_ptr: Pointer to the hand-off data
* Return: 0 on success, a negative errno on failure
*/
int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params,
struct mmc_device_info *info);
int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
unsigned int width, unsigned int flags,
struct mmc_device_info *device_info);
void sdmmc_pin_config(void);
size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size);
size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size);
int sdmmc_device_state(void);
bool is_cmd23_enabled(void);
int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
unsigned int r_type, unsigned int *r_data);
#endif

12
plat/intel/soc/common/socfpga_storage.c
View file

@ -22,22 +22,12 @@
#include <drivers/partition/partition.h>
#include <lib/mmio.h>
#include <tools_share/firmware_image_package.h>
#include "drivers/sdmmc/sdmmc.h"
#include "socfpga_private.h"
#include "socfpga_ros.h"
#define PLAT_FIP_BASE (0)
# if ARM_LINUX_KERNEL_AS_BL33
#define PLAT_FIP_MAX_SIZE (0x8000000)
#define PLAT_MMC_DATA_BASE (0x10000000)
#define PLAT_MMC_DATA_SIZE (0x100000)
# else
#define PLAT_FIP_MAX_SIZE (0x1000000)
#define PLAT_MMC_DATA_BASE (0xffe3c000)
#define PLAT_MMC_DATA_SIZE (0x2000)
# endif
static const io_dev_connector_t *fip_dev_con;
static const io_dev_connector_t *boot_dev_con;

10
plat/intel/soc/n5x/include/socfpga_plat_def.h
View file

@ -30,12 +30,14 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
/* FIP Setting */
#define PLAT_FIP_BASE (0)
#define PLAT_FIP_MAX_SIZE (0x1000000)
/* SDMMC Setting */
# if ARM_LINUX_KERNEL_AS_BL33
#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
# else
#define PLAT_MMC_DATA_BASE (0xffe3c000)
#define PLAT_MMC_DATA_SIZE (0x2000)
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
# endif
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000)

10
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -29,12 +29,14 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
/* FIP Setting */
#define PLAT_FIP_BASE (0)
#define PLAT_FIP_MAX_SIZE (0x1000000)
/* SDMMC Setting */
# if ARM_LINUX_KERNEL_AS_BL33
#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
# else
#define PLAT_MMC_DATA_BASE (0xffe3c000)
#define PLAT_MMC_DATA_SIZE (0x2000)
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
# endif
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000