For ST STM32MP15 boards, where the default BL32 is OP-TEE, we add new
versions of DT files with -sp_min.dts extension to manage this
configuration. These files can be compiled directly, or, with the
previous patch, the same command line can be used and those sp_min
files will be automatically used, if AARCH32_SP=sp_min option is used.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I5aabe415b0302da48f02918a3dbd24f334eb8e7d
The current code is incredibly resilient to updates to the spec and
has worked quite well so far. However, recent implementations expose a
weakness in that this is rather slow. A large part of it is written in
assembly, making it opaque to the compiler for optimisations. The
future proofness requires reading registers that are effectively
`volatile`, making it even harder for the compiler, as well as adding
lots of implicit barriers, making it hard for the microarchitecutre to
optimise as well.
We can make a few assumptions, checked by a few well placed asserts, and
remove a lot of this burden. For a start, at the moment there are 4
group 0 counters with static assignments. Contexting them is a trivial
affair that doesn't need a loop. Similarly, there can only be up to 16
group 1 counters. Contexting them is a bit harder, but we can do with a
single branch with a falling through switch. If/when both of these
change, we have a pair of asserts and the feature detection mechanism to
guard us against pretending that we support something we don't.
We can drop contexting of the offset registers. They are fully
accessible by EL2 and as such are its responsibility to preserve on
powerdown.
Another small thing we can do, is pass the core_pos into the hook.
The caller already knows which core we're running on, we don't need to
call this non-trivial function again.
Finally, knowing this, we don't really need the auxiliary AMUs to be
described by the device tree. Linux doesn't care at the moment, and any
information we need for EL3 can be neatly placed in a simple array.
All of this, combined with lifting the actual saving out of assembly,
reduces the instructions to save the context from 180 to 40, including a
lot fewer branches. The code is also much shorter and easier to read.
Also propagate to aarch32 so that the two don't diverge too much.
Change-Id: Ib62e6e9ba5be7fb9fb8965c8eee148d5598a5361
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
MPMM is a core-specific microarchitectural feature. It has been present
in every Arm core since the Cortex-A510 and has been implemented in
exactly the same way. Despite that, it is enabled more like an
architectural feature with a top level enable flag. This utilised the
identical implementation.
This duality has left MPMM in an awkward place, where its enablement
should be generic, like an architectural feature, but since it is not,
it should also be core-specific if it ever changes. One choice to do
this has been through the device tree.
This has worked just fine so far, however, recent implementations expose
a weakness in that this is rather slow - the device tree has to be read,
there's a long call stack of functions with many branches, and system
registers are read. In the hot path of PSCI CPU powerdown, this has a
significant and measurable impact. Besides it being a rather large
amount of code that is difficult to understand.
Since MPMM is a microarchitectural feature, its correct placement is in
the reset function. The essence of the current enablement is to write
CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C
enablement with an assembly macro in each CPU's reset function achieves
the same effect with just a single close branch and a grand total of 6
instructions (versus the old 2 branches and 32 instructions).
Having done this, the device tree entry becomes redundant. Should a core
that doesn't support MPMM arise, this can cleanly be handled in the
reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks
mechanisms become obsolete and are removed.
Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change size of PCIe memory region 2 from 256GB
to 3GB to fit in 1TB of GPT PPS.
Change-Id: Ic769bb784dd17d390b54ccef53b7788334373cb4
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Update RMMD_MANIFEST_VERSION_MINOR from 3 to 4.
- Read PCIe related information from DTB and write it to
Boot manifest.
- Rename structures that used to describe DRAM layout
and now describe both DRAM and PCIe IO memory regions:
- ns_dram_bank -> memory_bank
- ns_dram_info -> memory_info.
Change-Id: Ib75d1af86076f724f5c330074e231f1c2ba8e21d
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3): define SPMC manifest base address
feat(arm): add a macro for SPMC manifest base address
feat(rdv3): add carveout for BL32 image
feat(rdv3): introduce platform handler for Group0 interrupt
feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled
fix(neoverse-rd): set correct SVE vector lengths
Enable the Arm SPE DT binding for TC4.
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I9ea49046a663eecc2b97ecef9ca939575d71fdd9
On RD-V3 platform and variants, Hafnium is used as SPMC running at
S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured
as BL32 image. SP is loaded by SP load framework and configured by
Hafnium.
Add the dts files needed to enable load and configuration of hafnium and
SP.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I7de72052323ff9106d7bedbaaf5ece3272e9a6cd
* changes:
feat(tc): get entropy with PSA Crypto API
feat(psa): add interface with RSE for retrieving entropy
fix(psa): guard Crypto APIs with CRYPTO_SUPPORT
feat(tc): enable trng
feat(tc): initialize the RSE communication in earlier phase
Enable the trng on the platform, which can be used by other features.
`rng-seed` has been removed and enabled `FEAT_RNG_TRAP` to trap to EL3
when accessing system registers RNDR and RNDRRS
Change-Id: Ibde39115f285e67d31b14863c75beaf37493deca
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
These specify the addresses of the MPAM registers in the MCN block. Note
that these are enabled for TC4 FPGA only as the MPAM devices are not
available on FVP.
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I105cd21952c2bd4fac5a06c84c0a93217b5e1312
This node specifies the location of the MPAM registers for the DSU.
Rename the node to clarify this.
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ie870a7f31acbc44dd943e76896219b9bbdd7d5b4
CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU node per microarchitecture.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibbe8dacda695ccb45965c7f4680d4b03cffdb815
Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.
Change-Id: I70b68b06501d17dcebbe78bee8fec0a701106c92
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Modify ethernet base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.
Change-Id: I7b180c3eb90d7557d0011a25a742106f703cd264
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.
Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.
Change-Id: Ie31933e0bcbd489945935829940a5c5434e6b1d7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Modify mmc base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.
Change-Id: Ie8fe1f1d3aef1c020ac85db7c3b81dfad3722e2f
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
As per GPU team, this change should be helpful to improve
the performance.
Change-Id: I10a3fc1d0ddf1ba0a17da6dc4f2a80f5fe567db6
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Currently used stream id 0x200 gives below fault,
[ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000000000
[ 9.547393][ C0] raw fault status: 0x400D02C0
[ 9.547393][ C0] exception type 0xC0: TRANSLATION_FAULT at level 0
[ 9.547393][ C0] access type 0x2: READ
As per the GPU team, GPU stream id is 0 on TC4-FPGA so change it.
Change-Id: I3aed62289c5b96fb850f0022ea7f5172c606eb95
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.
Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
New slew rate applied.
SDMMC:
- for SD card and eMMC:
- clk at 2.
- cmd and data at 1.
- for Wifi
- clk at 1.
- cmd and data at 0.
SDMMC1:
- for dk board:
- clk at 2.
- cmd and data at 1.
- for eval board:
- clk at 3.
- cmd and data at 2.
Change-Id: I2dfa62aca08a613e0532746050246fc8dc476ff8
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
These DT files will be used by STM32MP2 boards. They embed DDR
parameters for LPDDR4 1x16Gb 1*32bits, at 800MHz or 1200MHz.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4017e44b3e9d01735d76518666d05405c2bd976b
* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure access to pmu counters on TC4
feat(tc): define MCN related macros for TC4
Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1a85ba646604336ce3f16c28171589af78f65251
Add 'kaslr-seed' node in device tree for TC3.
Note, TC4 doesn't need to add this node as it can dynamically generate
seed based on CPU arch's RNG_TRAP feature.
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I5c3f857d0f4e81ccd3bacb4c1ab032c8ea6e6873
On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7
These dts nodes are used by u-boot MHU/RSE driver to faciliate
communication with RSE over MHU.
FPGA doesn't seem to have the MHU instances which are used to
communicate with RSE so keep rse mhu disabled for fpga.
Signed-off-by: Yu Shihai <yu.shihai@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib10b3da09626e5beb6d6cd87b1618a143234a5d0
Add DSU PMU node for TC4. DSU PMU interrupt is not connected on TC3
but it is connected on IRQ 290 on TC4, so add interrupt property
specifically for TC4.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib1b810df65004987e9f3cf1bbd5deb5d211f3a17
The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")
To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.
We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d
Fix issues in RD1-AE flattened device tree source
- Update GIC GICR register region size to 0x40_0000.
GICR region size = 16 (RDcount) * 64KB frame size * 4 (with GIC v4.1)
- Update cpu_on function ID in psci node.
Use SMC64 version function ID 0xc4000003 instead. Although this
property doesn't actually take effect, align its value with
cpu_suspend selection to avoid any confusion.
Change-Id: Ib0840db45d32f0c8f1eb7dc74dc7d9b4ca6de0c3
Signed-off-by: David Hu <david.hu2@arm.com>
Add a node for AP_REFCLK Non-Secure Generic Timer in device tree, which
acts as a system timer to fix the failure of SystemReady IR ACS BSA
test case 402.
Refer to https://github.com/ARM-software/bsa-acs/blob/v23.09_REL1.0.6\
/docs/arm_bsa_testcase_checklist.rst?plain=1#L115
for more information.
Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Change-Id: I3e63a5ecfd8c6211f917ca3844b8b7bda208d83a
This clock name was renamed from MCO2_PLL4P to MCO2_PLL4 with the RCC
binding update commit [1]. This file was missed in that update, and the
board fails to compile.
[1]: 52b253bfa2 feat(dt-bindings): new RCC DT bindings
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I215abff1fc275ac1ef6dfb2ac86b9223e6990064
Change the interrupt name "combined-mbx" to "combined", which is the
correct naming defined in the mainline kernel.
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: I8d2da2dd0e9dac2bed3963efc695a277bb5e14bd
BL31 will need to access a device tree for several configurations (UART,
GIC, OTP mapping...).
Create a BL31 device tree (SOC_FW_CONFIG). It is loaded in DDR, in a
spare area.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I320a05859e1aa3dd8db9a274e7201075a8c250c2
Add include for DDR configuration, and reference to OTP storing the
board ID.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie2d5272ecf1dac77b91b2c148ec4dc1fb7b76631
These DT files will be used by STM32MP2 boards. They embed DDR parameters
for DDR4 2x8Gb 2*16bits, at 800MHz or 1200MHz.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iec73f9c5028f897624125082bdb591274aad3afc
Complete DDR node with all necessary DDRCTRL (register values) and
DDRPHY (user input values) settings.
Add also name and speed properties.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ie63f48dcacefe590c68cf6ec694d9e82349cece8
Add the required power supplies for DDR nodes. The power supplies are
provided by STPMIC2 regulators.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I951da75a554bc4fbfbc69ea9cd1171d99ed7ce46
