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fix(tc): modify DPU configuration in dts for TC4 FPGA

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TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.

Change-Id: Ie31933e0bcbd489945935829940a5c5434e6b1d7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
This commit is contained in:
Jagdish Gediya 2024-07-01 05:29:19 +00:00 • committed by Icen.Zeyada
parent ba1faaf117
commit bb9b89366f
3 changed files with 11 additions and 3 deletions

4
fdts/tc3-4-base.dtsi
View file

@ -22,10 +22,8 @@
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-base.dtsi"
/ {

5
fdts/tc3.dts
View file

@ -40,6 +40,11 @@
#define VIRTIO_BLOCK_ADDR 1c130000
#define VIRTIO_BLOCK_INT 204
#if TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"

5
fdts/tc4.dts
View file

@ -46,6 +46,11 @@
#define VIRTIO_BLOCK_ADDR 60020000
#define VIRTIO_BLOCK_INT 769
#if TARGET_FLAVOUR_FPGA
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#endif
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"