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refactor(tc): clarify msc0 DT node

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This node specifies the location of the MPAM registers for the DSU.
Rename the node to clarify this.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ie870a7f31acbc44dd943e76896219b9bbdd7d5b4
This commit is contained in:
Jackson Cooper-Driver 2024-08-28 11:46:35 +01:00 • committed by Icen.Zeyada
parent 4c23d62746
commit 967999d0d9
3 changed files with 4 additions and 4 deletions
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4
fdts/tc-base.dtsi
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@ -615,9 +615,9 @@
* L3 cache in the DSU is the Memory System Component (MSC)
* The MPAM registers are accessed through utility bus in the DSU
*/
msc0 {
dsu-msc0 {
compatible = "arm,mpam-msc";
reg = <MPAM_ADDR 0x0 0x2000>;
reg = <DSU_MPAM_ADDR 0x0 0x2000>;
};
ete0 {

2
fdts/tc2.dts
View file

@ -35,7 +35,7 @@
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define DSU_MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69

2
fdts/tc3-4-base.dtsi
View file

@ -17,7 +17,7 @@
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define DSU_MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000