mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-07 13:23:55 +00:00
feat(stm32mp15-fdts): add SP_MIN versions of DT files
For ST STM32MP15 boards, where the default BL32 is OP-TEE, we add new versions of DT files with -sp_min.dts extension to manage this configuration. These files can be compiled directly, or, with the previous patch, the same command line can be used and those sp_min files will be automatically used, if AARCH32_SP=sp_min option is used. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I5aabe415b0302da48f02918a3dbd24f334eb8e7d
This commit is contained in:
Yann Gautier
parent
71ba1647e0
commit
20544d66cc
10 changed files with 301 additions and 68 deletions
7
fdts/stm32mp157a-dk1-sp_min-fw-config.dts
Normal file
7
fdts/stm32mp157a-dk1-sp_min-fw-config.dts
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define DDR_SIZE 0x20000000 /* 512MB */
|
||||
#include "stm32mp15-fw-config.dtsi"
|
||||
69
fdts/stm32mp157a-dk1-sp_min.dts
Normal file
69
fdts/stm32mp157a-dk1-sp_min.dts
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#include "stm32mp157a-dk1.dts"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board (SP_MIN)";
|
||||
};
|
||||
|
||||
&rcc {
|
||||
st,clksrc = <
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
CLK_CKPER_HSE
|
||||
CLK_FMC_ACLK
|
||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_PLL4P
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_CSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
DIV(DIV_MPU, 1)
|
||||
DIV(DIV_AXI, 0)
|
||||
DIV(DIV_MCU, 0)
|
||||
DIV(DIV_APB1, 1)
|
||||
DIV(DIV_APB2, 1)
|
||||
DIV(DIV_APB3, 1)
|
||||
DIV(DIV_APB4, 1)
|
||||
DIV(DIV_APB5, 2)
|
||||
DIV(DIV_MCO1, 0)
|
||||
DIV(DIV_MCO2, 0)
|
||||
>;
|
||||
};
|
||||
7
fdts/stm32mp157c-dk2-sp_min-fw-config.dts
Normal file
7
fdts/stm32mp157c-dk2-sp_min-fw-config.dts
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define DDR_SIZE 0x20000000 /* 512MB */
|
||||
#include "stm32mp15-fw-config.dtsi"
|
||||
69
fdts/stm32mp157c-dk2-sp_min.dts
Normal file
69
fdts/stm32mp157c-dk2-sp_min.dts
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#include "stm32mp157c-dk2.dts"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board (SP_MIN)";
|
||||
};
|
||||
|
||||
&rcc {
|
||||
st,clksrc = <
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
CLK_CKPER_HSE
|
||||
CLK_FMC_ACLK
|
||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_PLL4P
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_CSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
DIV(DIV_MPU, 1)
|
||||
DIV(DIV_AXI, 0)
|
||||
DIV(DIV_MCU, 0)
|
||||
DIV(DIV_APB1, 1)
|
||||
DIV(DIV_APB2, 1)
|
||||
DIV(DIV_APB3, 1)
|
||||
DIV(DIV_APB4, 1)
|
||||
DIV(DIV_APB5, 2)
|
||||
DIV(DIV_MCO1, 0)
|
||||
DIV(DIV_MCO2, 0)
|
||||
>;
|
||||
};
|
||||
7
fdts/stm32mp157c-ed1-sp_min-fw-config.dts
Normal file
7
fdts/stm32mp157c-ed1-sp_min-fw-config.dts
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define DDR_SIZE 0x40000000 /* 1GB */
|
||||
#include "stm32mp15-fw-config.dtsi"
|
||||
69
fdts/stm32mp157c-ed1-sp_min.dts
Normal file
69
fdts/stm32mp157c-ed1-sp_min.dts
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#include "stm32mp157c-ed1.dts"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C eval daughter (SP_MIN)";
|
||||
};
|
||||
|
||||
&rcc {
|
||||
st,clksrc = <
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
CLK_CKPER_HSE
|
||||
CLK_FMC_ACLK
|
||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_PLL4P
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_CSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
DIV(DIV_MPU, 1)
|
||||
DIV(DIV_AXI, 0)
|
||||
DIV(DIV_MCU, 0)
|
||||
DIV(DIV_APB1, 1)
|
||||
DIV(DIV_APB2, 1)
|
||||
DIV(DIV_APB3, 1)
|
||||
DIV(DIV_APB4, 1)
|
||||
DIV(DIV_APB5, 2)
|
||||
DIV(DIV_MCO1, 0)
|
||||
DIV(DIV_MCO2, 0)
|
||||
>;
|
||||
};
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
|
@ -195,43 +195,13 @@
|
|||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
CLK_CKPER_HSE
|
||||
CLK_FMC_ACLK
|
||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_PLL4P
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_CSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
|
|
@ -244,8 +214,6 @@
|
|||
DIV(DIV_APB4, 1)
|
||||
DIV(DIV_APB5, 2)
|
||||
DIV(DIV_RTC, 23)
|
||||
DIV(DIV_MCO1, 0)
|
||||
DIV(DIV_MCO2, 0)
|
||||
>;
|
||||
|
||||
st,pll_vco {
|
||||
|
|
|
|||
7
fdts/stm32mp157c-ev1-sp_min-fw-config.dts
Normal file
7
fdts/stm32mp157c-ev1-sp_min-fw-config.dts
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define DDR_SIZE 0x40000000 /* 1GB */
|
||||
#include "stm32mp15-fw-config.dtsi"
|
||||
64
fdts/stm32mp157c-ev1-sp_min.dts
Normal file
64
fdts/stm32mp157c-ev1-sp_min.dts
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c-ed1-sp_min.dts"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C eval daughter on eval mother (SP_MIN)";
|
||||
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
serial1 = &usart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&fmc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&fmc_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
nand-controller@4,0 {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-on-flash-bbt;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi_clk_pins_a
|
||||
&qspi_bk1_pins_a
|
||||
&qspi_cs1_pins_a>;
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash0: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&usart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usart3_pins_b>;
|
||||
uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2019-2024, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (c) 2019-2025, STMicroelectronics - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
|
|
@ -199,43 +199,11 @@
|
|||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
CLK_CKPER_HSE
|
||||
CLK_FMC_ACLK
|
||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_PLL4P
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_CSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
|
|
@ -248,8 +216,6 @@
|
|||
DIV(DIV_APB4, 1)
|
||||
DIV(DIV_APB5, 2)
|
||||
DIV(DIV_RTC, 23)
|
||||
DIV(DIV_MCO1, 0)
|
||||
DIV(DIV_MCO2, 0)
|
||||
>;
|
||||
|
||||
st,pll_vco {
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue