Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-07 21:33:54 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

feat(rdv3): add dts files to enable hafnium as BL32

Browse source 
On RD-V3 platform and variants, Hafnium is used as SPMC running at
S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured
as BL32 image. SP is loaded by SP load framework and configured by
Hafnium.

Add the dts files needed to enable load and configuration of hafnium and
SP.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I7de72052323ff9106d7bedbaaf5ece3272e9a6cd
This commit is contained in:
Nishant Sharma 2023-09-14 09:14:03 +01:00 • committed by Rakshit Goyal
parent 12973bcc89
commit 4d9b8281f3
5 changed files with 146 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

37
fdts/rdv3-defs.dtsi Normal file
View file

@ -0,0 +1,37 @@
/*
* Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RD_V3_DEFS_DTSI
#define RD_V3_DEFS_DTSI
#define CONCAT(x, y) x##y
#define CONC(x, y) CONCAT(x, y)
#define ADR(n) \
CPU##n:cpu@n##0000 {
#define PRE \
device_type = "cpu"; \
compatible = "arm,armv8";
#define CPU_0 \
CPU0:cpu@0 { \
PRE \
reg = <0x0 0x0>;\
};
#define POST };
/*
* n - CPU number
*/
#define CPU(n) \
ADR(n) \
PRE \
reg = <0x0 CONC(0x, CONC(n, 0000))>; \
POST
#endif /* RD_V3_DEFS_DTSI */

9
plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -18,6 +18,13 @@
id = <TB_FW_CONFIG_ID>;
};
tos_fw-config {
load-address = <0x0 0x01f500>;
secondary-load-address = <0x0 0xF9200000>;
max-size = <0x1000>;
id = <TOS_FW_CONFIG_ID>;
};
nt_fw-config {
load-address = <0x0 0xF3000000>;
max-size = <0x0100000>;

85
plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_spmc_sp_manifest.dts Normal file
View file

@ -0,0 +1,85 @@
/*
* Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#define AFF 00
#include "rdv3-defs.dtsi"
/ {
compatible = "arm,ffa-core-manifest-1.0";
#address-cells = <2>;
#size-cells = <2>;
attribute {
spmc_id = <0x8000>;
maj_ver = <0x1>;
min_ver = <0x1>;
exec_state = <0x0>;
load_address = <0x0 0xfa889000>;
entrypoint = <0x0 0xfa889000>;
binary_size = <0x177000>;
};
hypervisor {
compatible = "hafnium,hafnium";
vm1 {
is_ffa_partition;
debug_name = "stmm";
load_address = <0xFAA00000>;
vcpu_count = <1>;
mem_size = <0x300000>;
};
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
CPU_0
/*
* SPMC (Hafnium) requires secondary core nodes are declared
* in descending order.
*/
#if (NRD_PLATFORM_VARIANT != 1)
CPU(F)
CPU(E)
CPU(D)
CPU(C)
CPU(B)
CPU(A)
CPU(9)
CPU(8)
#endif
CPU(7)
CPU(6)
CPU(5)
CPU(4)
CPU(3)
CPU(2)
CPU(1)
};
memory@0 {
device_type = "memory";
reg = /* Trusted DRAM for SPMC and SP */
<0x0 0xfa889000 0x0 0x400000
/* Trusted DRAM for SP Heap*/
0x0 0xfad00000 0x0 0x500000>;
};
memory@1 {
device_type = "ns-memory";
/* DRAM for SP NS mappings*/
reg = <0x0 0x80000000 0x0 0x78FE0000>;
};
memory@2 {
device_type = "device-memory";
reg = /* AP Memory Expansion 2 - Secure Flash*/
<0x6 0x04000000 0x0 0x04000000>;
};
};

11
plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -25,4 +25,13 @@
mbedtls_heap_addr = <0x0 0x0>;
mbedtls_heap_size = <0x0>;
};
secure-partitions {
compatible = "arm,sp";
stmm {
uuid = "eaba83d8-baaf-4eaf-8144-f7fdcbe544a7";
load-address = <0xFAA00000>;
owner = "Plat";
};
};
};

6
plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
View file

@ -136,6 +136,12 @@ FDT_SOURCES += ${RDV3_BASE}/fdts/${PLAT}_fw_config.dts \
${RDV3_BASE}/fdts/${PLAT}_tb_fw_config.dts \
${RDV3_BASE}/fdts/${PLAT}_nt_fw_config.dts
ifeq (${SPMD_SPM_AT_SEL2}, 1)
BL32_CONFIG_DTS := ${RDV3_BASE}/fdts/${PLAT}_spmc_sp_manifest.dts
FDT_SOURCES += ${BL32_CONFIG_DTS}
TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${BL32_CONFIG_DTS})).dtb
endif
FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb