From 4d9b8281f35256f7367a6b76b1259d9edbefe713 Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Thu, 14 Sep 2023 09:14:03 +0100 Subject: [PATCH] feat(rdv3): add dts files to enable hafnium as BL32 On RD-V3 platform and variants, Hafnium is used as SPMC running at S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured as BL32 image. SP is loaded by SP load framework and configured by Hafnium. Add the dts files needed to enable load and configuration of hafnium and SP. Signed-off-by: Nishant Sharma Signed-off-by: Rohit Mathew Signed-off-by: Rakshit Goyal Change-Id: I7de72052323ff9106d7bedbaaf5ece3272e9a6cd --- fdts/rdv3-defs.dtsi | 37 ++++++++ .../platform/rdv3/fdts/rdv3_fw_config.dts | 9 +- .../rdv3/fdts/rdv3_spmc_sp_manifest.dts | 85 +++++++++++++++++++ .../platform/rdv3/fdts/rdv3_tb_fw_config.dts | 11 ++- .../neoverse_rd/platform/rdv3/platform.mk | 6 ++ 5 files changed, 146 insertions(+), 2 deletions(-) create mode 100644 fdts/rdv3-defs.dtsi create mode 100644 plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_spmc_sp_manifest.dts diff --git a/fdts/rdv3-defs.dtsi b/fdts/rdv3-defs.dtsi new file mode 100644 index 000000000..0ec4ccc60 --- /dev/null +++ b/fdts/rdv3-defs.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RD_V3_DEFS_DTSI +#define RD_V3_DEFS_DTSI + +#define CONCAT(x, y) x##y +#define CONC(x, y) CONCAT(x, y) + +#define ADR(n) \ + CPU##n:cpu@n##0000 { + +#define PRE \ + device_type = "cpu"; \ + compatible = "arm,armv8"; + +#define CPU_0 \ + CPU0:cpu@0 { \ + PRE \ + reg = <0x0 0x0>;\ + }; + +#define POST }; + +/* + * n - CPU number + */ +#define CPU(n) \ + ADR(n) \ + PRE \ + reg = <0x0 CONC(0x, CONC(n, 0000))>; \ + POST + +#endif /* RD_V3_DEFS_DTSI */ diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts index 62ba0fad2..7a904fec7 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts +++ b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,6 +18,13 @@ id = ; }; + tos_fw-config { + load-address = <0x0 0x01f500>; + secondary-load-address = <0x0 0xF9200000>; + max-size = <0x1000>; + id = ; + }; + nt_fw-config { load-address = <0x0 0xF3000000>; max-size = <0x0100000>; diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_spmc_sp_manifest.dts b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_spmc_sp_manifest.dts new file mode 100644 index 000000000..c9764e463 --- /dev/null +++ b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_spmc_sp_manifest.dts @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +#define AFF 00 + +#include "rdv3-defs.dtsi" + +/ { + compatible = "arm,ffa-core-manifest-1.0"; + #address-cells = <2>; + #size-cells = <2>; + + attribute { + spmc_id = <0x8000>; + maj_ver = <0x1>; + min_ver = <0x1>; + exec_state = <0x0>; + load_address = <0x0 0xfa889000>; + entrypoint = <0x0 0xfa889000>; + binary_size = <0x177000>; + }; + + hypervisor { + compatible = "hafnium,hafnium"; + vm1 { + is_ffa_partition; + debug_name = "stmm"; + load_address = <0xFAA00000>; + vcpu_count = <1>; + mem_size = <0x300000>; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU_0 + + /* + * SPMC (Hafnium) requires secondary core nodes are declared + * in descending order. + */ +#if (NRD_PLATFORM_VARIANT != 1) + CPU(F) + CPU(E) + CPU(D) + CPU(C) + CPU(B) + CPU(A) + CPU(9) + CPU(8) +#endif + CPU(7) + CPU(6) + CPU(5) + CPU(4) + CPU(3) + CPU(2) + CPU(1) + }; + + memory@0 { + device_type = "memory"; + reg = /* Trusted DRAM for SPMC and SP */ + <0x0 0xfa889000 0x0 0x400000 + /* Trusted DRAM for SP Heap*/ + 0x0 0xfad00000 0x0 0x500000>; + }; + + memory@1 { + device_type = "ns-memory"; + /* DRAM for SP NS mappings*/ + reg = <0x0 0x80000000 0x0 0x78FE0000>; + }; + memory@2 { + device_type = "device-memory"; + reg = /* AP Memory Expansion 2 - Secure Flash*/ + <0x6 0x04000000 0x0 0x04000000>; + }; +}; diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts index a4c7c7286..77c47250d 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts +++ b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,4 +25,13 @@ mbedtls_heap_addr = <0x0 0x0>; mbedtls_heap_size = <0x0>; }; + + secure-partitions { + compatible = "arm,sp"; + stmm { + uuid = "eaba83d8-baaf-4eaf-8144-f7fdcbe544a7"; + load-address = <0xFAA00000>; + owner = "Plat"; + }; + }; }; diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk index b05b1f819..bae940cad 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk +++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk @@ -136,6 +136,12 @@ FDT_SOURCES += ${RDV3_BASE}/fdts/${PLAT}_fw_config.dts \ ${RDV3_BASE}/fdts/${PLAT}_tb_fw_config.dts \ ${RDV3_BASE}/fdts/${PLAT}_nt_fw_config.dts +ifeq (${SPMD_SPM_AT_SEL2}, 1) +BL32_CONFIG_DTS := ${RDV3_BASE}/fdts/${PLAT}_spmc_sp_manifest.dts +FDT_SOURCES += ${BL32_CONFIG_DTS} +TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${BL32_CONFIG_DTS})).dtb +endif + FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb