This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame. Testing was
conducted by:
* Manual comparison of disassembly of converted functions with non-
converted functions.
aarch64-none-elf-objdump -D <TF-A with
conversion>/build/../release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <TF-A clean
repo>/build/fvp/release/bl31/bl31.elf
* Build for release with all errata flags enabled and compare
the disassembly of converted functions with non-converted
functions.
CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp DEBUG=0 \
HW_ASSISTED_COHERENCY=0 BL33=<tf-a-tests>/build/fvp/debug/tftf.bin \
all fip ERRATA_A73_852427=1 \
ERRATA_A73_855423=1 \
WORKAROUND_CVE_2017_5715=1 \
WORKAROUND_CVE_2018_3639=1 \
WORKAROUND_CVE_2022_23960=1
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Change-Id: I63e5b2cc42e1e12daee0b727770cbc19ba729ff7
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.
Change-Id: I70b05cc366c3b6d07a63edd88d23a52dd3d019c1
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame. Testing was
conducted by:
* Manual comparison of disassembly of converted functions with non-
converted functions.
aarch64-none-elf-objdump -D <TF-A with
conversion>/build/../release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <TF-A with
clean repo>/build/fvp/release/bl31/bl31.elf
* Build for release with all errata flags enabled and ensure the
changes were identical.
CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp \
DEBUG=0 HW_ASSISTED_COHERENCY=0 \
BL33=<tf-a-tests>/build/fvp/debug/tftf.bin \
all fip ERRATA_A35_855472=1
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Change-Id: Ib001e9fc269e60369ccfda0245a3e6247f0d6aaa
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
* changes:
fix(cpus): workaround for Neoverse N2 erratum 2779511
fix(errata-abi): added Neoverse N2 to Errata ABI list
fix(cpus): workaround for Neoverse N2 erratum 2743014
fix(docs): updated certain Neoverse N2 erratum status in docs
refactor(cpus): convert Neoverse N2 to use CPU helpers
refactor(cpus): convert Neoverse N2 to framework
refactor(cpus): reorder Neoverse N2 errata by ascending order
* changes:
refactor(cpus): convert Neoverse V1 to use CPU helpers
refactor(cpus): convert Neoverse V1 to framework
refactor(cpus): reorder Neoverse V1 errata by ascending order
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Testing was conducted by:
* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata. Only
able to verify the check functions this way, rest had to manually
verified
* Manual comparison of disassembly of converted functions with non-
converted functions
aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
* Build for release with all errata flags enabled and run default tftf
tests
CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp DEBUG=0 \
CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 \
BL33=./../tf-a-tests/build/fvp/release/tftf.bin \
ERRATA_V1_1618635=1 ERRATA_V1_1774420=1 ERRATA_V1_1791573=1 \
ERRATA_V1_1852267=1 ERRATA_V1_1925756=1 ERRATA_V1_1940577=1 \
ERRATA_V1_1966096=1 ERRATA_V1_2108267=1 ERRATA_V1_2139242=1 \
ERRATA_V1_2216392=1 ERRATA_V1_2294912=1 ERRATA_V1_2372203=1 \
ERRATA_V1_2743093=1 ERRATA_V1_2743233=1 ERRATA_V1_2779461=1 \
WORKAROUND_CVE_2022_23960=1 ERRATA_ABI_SUPPORT=1 all fip
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic5697b7cd2a508dee9978d89136fbe168f34626c
* changes:
refactor(cpus): convert the Cortex-A55 to use cpu helpers
refactor(cpus): convert the Cortex-A55 to use the errata framework
refactor(cpus): convert the Cortex-A76AE to use cpu helpers
refactor(cpus): convert the Cortex-A76AE to use the errata framework
refactor(cpus): convert the Cortex-A78 to use cpu helpers
refactor(cpus): convert the Cortex-A78 to use the errata framework
refactor(cpus): reorder Cortex-A78 errata by ascending order
refactor(cpus): convert the Cortex-A78C to use cpu helpers
refactor(cpus): convert the Cortex-A78C to use the errata framework
refactor(cpus): reorder Cortex-A78C errata by ascending order
refactor(cpus): convert the Cortex-X1 to use cpu helpers
refactor(cpus): convert the Cortex-X1 to use the errata framework
refactor(cpus): reorder Cortex-X1 errata by ascending order
refactor(cpus): use cpu errata wrappers Cortex-A12 aarch32 cpu
refactor(cpus): use cpu errata wrappers Cortex-A7 and A9 aarch32 cpus
Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CPUACTLR3_EL1
SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iaa0e30de8473ecb1df1fcca3a45904aac2e419b3
added the missing Neoverse N2 flag required for
enabling Neoverse N2 CPU in Errata ABI
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I06c6fa67e2f1ccc053f1b1b9261e189c56f4347a
Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie7e1be5dea9d1f74738f9fed0fb58bfd41763192
Certain Neoverse N2 erratum in docs were out of date with the latest
SDEN document and hence updated it to match the latest
SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5d82a56388a46a09a42b940a633ecebdde0c74e3
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Testing was conducted by:
* Manual comparison of disassembly of converted functions with non-
converted functions
aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
* Build for release with all errata flags enabled and run default tftf
tests
CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp CTX_INCLUDE_AARCH32_REGS=0 \
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 \
BL33=./../tf-a-tests/build/fvp/debug/tftf.bin \
ERRATA_N2_2002655=1 ERRATA_N2_2025414=1 ERRATA_N2_2067956=1 ERRATA_N2_2189731=1 \
ERRATA_N2_2138956=1 ERRATA_N2_2138953=1 ERRATA_N2_2242415=1 ERRATA_N2_2138958=1 \
ERRATA_N2_2242400=1 ERRATA_N2_2280757=1 ERRATA_N2_2326639=1 ERRATA_N2_2376738=1 \
ERRATA_N2_2388450=1 ERRATA_N2_2743014=1 ERRATA_N2_2743089=1 ERRATA_DSU_2313941=1 \
WORKAROUND_CVE_2022_23960=1 ERRATA_ABI_SUPPORT=1 all fip
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3dd06b5d827de5836eadd58ae28f28e62039f257
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Change-Id: I126f09de44b16e8bbb7e32477b880b4650eef23b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Change-Id: I2ff16be8bb568e37477edbbd7551877cbbde4c60
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I1936ab6aaef803f653e79f5c6b590a59b34a8ed1
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Change-Id: I41e4169fb16ef488e116f6b3b1b5cc78b070c0fb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Change-Id: Ib361cdfa43fc1c88d97e346d41b1cbf211c045d9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.
Change-Id: Ie3909ef51c28a24728752a08ddf96a48d87d3cd7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Adapt to use errata frame-work cpu macro helpers for Cortex-A12
aarch32 cpu.
Testing:
- Manual comparison of disassembly with and without the patch.
- Compile testing.
Change-Id: I9bad7f1e3d87419c0451b5d46edf0c406d31a84d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Adapt to use errata frame-work cpu macro helpers for following cpu's:
- Cortex-A7
- Cortex-A9
Testing:
- Manual comparison of disassembly with and without the patch.
- Compile testing.
Change-Id: I88eb90d7fd0e82fc4bfc9d1aee947f0c820e1222
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the TF-A it is already returning an error when there is any request
to access these APIs. So, just removing the unused code to avoid the
confusion around these APIs.
Also, there is no issue with the backward compatibility as these APIs
were never used since implemented. Hence no need to bump up the
version of the feature check API as well.
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Change-Id: I444f973e62cd25aae2e7f697d808210b265106ad
Deprecate pack_realm build command for TFTF.
To build Realm payload tests use ENABLE_REALM_PAYLOAD_TESTS=1.
This new command line for TFTF is effective from SHA 9945bef6b
in tf-a-tests repo.
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: Iee9ac9b2b367aac50677fac95631e7e4818cdf3a
Switch from IMX_BOOT_UART_BASE=0 to IMX_BOOT_UART_BASE=auto to make it
more obvious that the detection is based on the runtime autodetection.
In addition this moves the evaluation of IMX_BOOT_UART_BASE into the
makefile which removes the ugly conditional compilation as well.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I92c13607bf81c6267f4b6aee829d74902b7f72d2
* changes:
feat(rdn2): enable Neoverse N2 CPU error handling support
feat(sgi): firmware first error handling for Neoverse N2 CPU
feat(arm): enable FHI PPI interrupt to report CPU errors
RD-N2 platform variants have Neoverse N2 CPU that supports RAS
extensions. N2 CPU has error node that captures the faults occurring on
L1, L2 tag and data RAMs. This node captures the error information in
its error records and generates fault handling interrupt on error event.
This patch adds reference implementation to demonstrate firmware-first
error handling of 1-bit CE that occur on CPU. On error event the error
handler reads the error records and ELx context information and forwards
it to secure partition. Secure partition creates a CPER record from this
error information. Finally the handler notifies the OS about the RAS
error using the SDEI notification mechanism.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I769550efee10b9a3d89056bca4bfeb2db4708998
To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framework is initialized, only primary core is up and hence core FHI PPI
interrupt is enabled only on primary core. This patch adds support to
configure and enable core FHI interrupt for all the secondary cores as
part of their boot sequence.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4b25152cb498fe975b9c770babb25aa9e01f9656
* changes:
refactor(cpus): convert Cortex-A72 to use cpu helpers
refactor(cpus): convert the Cortex-A72 to use the errata framework
refactor(cpus): reorder Cortex-A72 errata by ascending order
On systems with SCP (running crust) scpi_system_reboot action
performs board-level (PMIC) reboot. This doesn't preserve RAM content
on A64 PinePhone at least.
warm/soft system reset without RAM reset is required to get
pstore (persistent storage) in RAM working with Linux kernel. That is
very useful for oops/panic logging for post mortem analysis.
scpi_system_reset action performs reset via SoC reset (using watchdog)
and RAM content is preserved in this case. Linux kernel detects
system_reset2 support and uses it for warm reset automatically.
Change-Id: I1c21aa8f27c8e0395e2326034788693b59b80bc4
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
