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Merge changes from topic "gr/errata_refactor" into integration

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* changes:
  refactor(cpus): convert the Cortex-A55 to use cpu helpers
  refactor(cpus): convert the Cortex-A55 to use the errata framework
  refactor(cpus): convert the Cortex-A76AE to use cpu helpers
  refactor(cpus): convert the Cortex-A76AE to use the errata framework
  refactor(cpus): convert the Cortex-A78 to use cpu helpers
  refactor(cpus): convert the Cortex-A78 to use the errata framework
  refactor(cpus): reorder Cortex-A78 errata by ascending order
  refactor(cpus): convert the Cortex-A78C to use cpu helpers
  refactor(cpus): convert the Cortex-A78C to use the errata framework
  refactor(cpus): reorder Cortex-A78C errata by ascending order
  refactor(cpus): convert the Cortex-X1 to use cpu helpers
  refactor(cpus): convert the Cortex-X1 to use the errata framework
  refactor(cpus): reorder Cortex-X1 errata by ascending order
  refactor(cpus): use cpu errata wrappers Cortex-A12 aarch32 cpu
  refactor(cpus): use cpu errata wrappers Cortex-A7 and A9 aarch32 cpus
This commit is contained in:
Bipin Ravi 2023-08-03 22:52:10 +02:00 • committed by TrustedFirmware Code Review
commit fc22bcf85c
8 changed files with 209 additions and 1232 deletions
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11
lib/cpus/aarch32/cortex_a12.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -69,14 +69,7 @@ func cortex_a12_cluster_pwr_dwn
b cortex_a12_disable_smp
endfunc cortex_a12_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex-A12. Must follow AAPCS.
*/
func cortex_a12_errata_report
bx lr
endfunc cortex_a12_errata_report
#endif
errata_report_shim cortex_a12
declare_cpu_ops cortex_a12, CORTEX_A12_MIDR, \
cortex_a12_reset_func, \

11
lib/cpus/aarch32/cortex_a7.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -69,14 +69,7 @@ func cortex_a7_cluster_pwr_dwn
b cortex_a7_disable_smp
endfunc cortex_a7_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex-A7. Must follow AAPCS.
*/
func cortex_a7_errata_report
bx lr
endfunc cortex_a7_errata_report
#endif
errata_report_shim cortex_a7
declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \
cortex_a7_reset_func, \

28
lib/cpus/aarch32/cortex_a9.S
View file

@ -35,14 +35,16 @@ func cortex_a9_enable_smp
bx lr
endfunc cortex_a9_enable_smp
func check_errata_a9_794073
func check_errata_794073
#if ERRATA_A9_794073
mov r0, #ERRATA_APPLIES
#else
mov r0, #ERRATA_MISSING
#endif
bx lr
endfunc check_errata_a9_794073
endfunc check_errata_794073
add_erratum_entry cortex_a9, ERRATUM(794073), ERRATA_A9_794073
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
@ -53,27 +55,9 @@ func check_errata_cve_2017_5715
bx lr
endfunc check_errata_cve_2017_5715
#if REPORT_ERRATA
/*
* Errata printing function for Cortex A9. Must follow AAPCS.
*/
func cortex_a9_errata_report
push {r12, lr}
add_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
bl cpu_get_rev_var
mov r4, r0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2017_5715, cortex_a9, cve_2017_5715
report_errata ERRATA_A9_794073, cortex_a9, a9_794073
pop {r12, lr}
bx lr
endfunc cortex_a9_errata_report
#endif
errata_report_shim cortex_a9
func cortex_a9_reset_func
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715

305
lib/cpus/aarch64/cortex_a55.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -18,63 +18,37 @@
.globl cortex_a55_reset_func
.globl cortex_a55_core_pwr_dwn
/* --------------------------------------------------
* Errata Workaround for Cortex A55 Errata #768277.
* This applies only to revision r0p0 of Cortex A55.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a55_768277_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_768277
cbz x0, 1f
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_768277_wa
func check_errata_768277
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_768277
/* ERRATA_DSU_798953:
* The errata is defined in dsu_helpers.S but applies to cortex_a55
* as well. Henceforth creating symbolic names to the already existing errata
* workaround functions to get them registered under the Errata Framework.
*/
.equ check_erratum_cortex_a55_798953, check_errata_dsu_798953
.equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa
add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
/* ------------------------------------------------------------------
* Errata Workaround for Cortex A55 Errata #778703.
* This applies only to revision r0p0 of Cortex A55 where L2 cache is
* not configured.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ------------------------------------------------------------------
*/
func errata_a55_778703_wa
/*
* Compare x0 against revision r0p0 and check that no private L2 cache
* is configured
*/
mov x17, x30
bl check_errata_778703
cbz x0, 1f
mrs x1, CORTEX_A55_CPUECTLR_EL1
orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL
msr CORTEX_A55_CPUECTLR_EL1, x1
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_778703_wa
/* ERRATA_DSU_936184:
* The errata is defined in dsu_helpers.S but applies to cortex_a55
* as well. Henceforth creating symbolic names to the already existing errata
* workaround functions to get them registered under the Errata Framework.
*/
.equ check_erratum_cortex_a55_936184, check_errata_dsu_936184
.equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa
add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
func check_errata_778703
workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
workaround_reset_end cortex_a55, ERRATUM(768277)
check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0)
workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703
sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL
sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
workaround_reset_end cortex_a55, ERRATUM(778703)
check_erratum_custom_start cortex_a55, ERRATUM(778703)
mov x16, x30
mov x1, #0x00
bl cpu_rev_var_ls
@ -87,111 +61,27 @@ func check_errata_778703
mov x2, #ERRATA_NOT_APPLIES
csel x0, x0, x2, eq
ret x16
endfunc check_errata_778703
check_erratum_custom_end cortex_a55, ERRATUM(778703)
/* --------------------------------------------------
* Errata Workaround for Cortex A55 Errata #798797.
* This applies only to revision r0p0 of Cortex A55.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a55_798797_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_798797
cbz x0, 1f
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_798797_wa
workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797
sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
workaround_reset_end cortex_a55, ERRATUM(798797)
func check_errata_798797
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_798797
check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
/* --------------------------------------------------------------------
* Errata Workaround for Cortex A55 Errata #846532.
* This applies only to revisions <= r0p1 of Cortex A55.
* Disabling dual-issue has a small impact on performance. Disabling a
* power optimization feature is an alternate workaround with no impact
* on performance but with an increase in power consumption (see errata
* notice).
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------------------------
*/
func errata_a55_846532_wa
/*
* Compare x0 against revision r0p1
*/
mov x17, x30
bl check_errata_846532
cbz x0, 1f
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_846532_wa
workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
workaround_reset_end cortex_a55, ERRATUM(846532)
func check_errata_846532
mov x1, #0x01
b cpu_rev_var_ls
endfunc check_errata_846532
check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1)
/* -----------------------------------------------------
* Errata Workaround for Cortex A55 Errata #903758.
* This applies only to revisions <= r0p1 of Cortex A55.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* -----------------------------------------------------
*/
func errata_a55_903758_wa
/*
* Compare x0 against revision r0p1
*/
mov x17, x30
bl check_errata_903758
cbz x0, 1f
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_903758_wa
workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758
sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
workaround_reset_end cortex_a55, ERRATUM(903758)
func check_errata_903758
mov x1, #0x01
b cpu_rev_var_ls
endfunc check_errata_903758
check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
/* -----------------------------------------------------
* Errata Workaround for Cortex A55 Errata #1221012.
* This applies only to revisions <= r1p0 of Cortex A55.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* -----------------------------------------------------
*/
func errata_a55_1221012_wa
/*
* Compare x0 against revision r1p0
*/
mov x17, x30
bl check_errata_1221012
cbz x0, 1f
workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
mov x0, #0x0020
movk x0, #0x0850, lsl #16
msr CPUPOR_EL3, x0
@ -214,121 +104,30 @@ func errata_a55_1221012_wa
mov x0, #0x03fd
movk x0, #0x0110, lsl #16
msr CPUPCR_EL3, x0
isb
1:
ret x17
endfunc errata_a55_1221012_wa
workaround_reset_end cortex_a55, ERRATUM(1221012)
func check_errata_1221012
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1221012
check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0)
/* --------------------------------------------------
* Errata workaround for Cortex A55 Errata #1530923.
* This applies to all revisions of Cortex A55.
* --------------------------------------------------
*/
func check_errata_1530923
#if ERRATA_A55_1530923
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_1530923
check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923
func cortex_a55_reset_func
mov x19, x30
/* erratum has no workaround in the cpu. Generic code must take care */
add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET
#if ERRATA_DSU_798953
bl errata_dsu_798953_wa
#endif
cpu_reset_func_start cortex_a55
cpu_reset_func_end cortex_a55
#if ERRATA_DSU_936184
bl errata_dsu_936184_wa
#endif
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A55_768277
mov x0, x18
bl errata_a55_768277_wa
#endif
#if ERRATA_A55_778703
mov x0, x18
bl errata_a55_778703_wa
#endif
#if ERRATA_A55_798797
mov x0, x18
bl errata_a55_798797_wa
#endif
#if ERRATA_A55_846532
mov x0, x18
bl errata_a55_846532_wa
#endif
#if ERRATA_A55_903758
mov x0, x18
bl errata_a55_903758_wa
#endif
#if ERRATA_A55_1221012
mov x0, x18
bl errata_a55_1221012_wa
#endif
ret x19
endfunc cortex_a55_reset_func
errata_report_shim cortex_a55
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_a55_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
mrs x0, CORTEX_A55_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK
msr CORTEX_A55_CPUPWRCTLR_EL1, x0
sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_a55_core_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex A55. Must follow AAPCS & can use stack.
*/
func cortex_a55_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision variant information is at x8, where
* "report_errata" is expecting it and it doesn't corrupt it.
*/
report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953
report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
report_errata ERRATA_A55_768277, cortex_a55, 768277
report_errata ERRATA_A55_778703, cortex_a55, 778703
report_errata ERRATA_A55_798797, cortex_a55, 798797
report_errata ERRATA_A55_846532, cortex_a55, 846532
report_errata ERRATA_A55_903758, cortex_a55, 903758
report_errata ERRATA_A55_1221012, cortex_a55, 1221012
report_errata ERRATA_A55_1530923, cortex_a55, 1530923
ldp x8, x30, [sp], #16
ret
endfunc cortex_a55_errata_report
#endif
/* ---------------------------------------------
* This function provides cortex_a55 specific
* register information for crash reporting.

61
lib/cpus/aarch64/cortex_a76ae.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -25,71 +25,34 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae
#endif /* WORKAROUND_CVE_2022_23960 */
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif /* WORKAROUND_CVE_2022_23960 */
ret
endfunc check_errata_cve_2022_23960
check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* --------------------------------------------
* The CPU Ops reset function for Cortex-A76AE.
* Shall clobber: x0-x19
* --------------------------------------------
*/
func cortex_a76ae_reset_func
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
* The Cortex-A76ae generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_a76ae
msr vbar_el3, x0
override_vector_table wa_cve_vbar_cortex_a76ae
isb
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_a76ae, CVE(2022, 23960)
ret
endfunc cortex_a76ae_reset_func
cpu_reset_func_start cortex_a76ae
cpu_reset_func_end cortex_a76ae
errata_report_shim cortex_a76ae
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_a76ae_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0
sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_a76ae_core_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex-A76AE. Must follow AAPCS.
*/
func cortex_a76ae_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2022_23960, cortex_a76ae, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a76ae_errata_report
#endif /* REPORT_ERRATA */
/* ---------------------------------------------
* This function provides cortex_a76ae specific
* register information for crash reporting.

493
lib/cpus/aarch64/cortex_a78.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -24,77 +24,25 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
#endif /* WORKAROUND_CVE_2022_23960 */
/* --------------------------------------------------
* Errata Workaround for A78 Erratum 1688305.
* This applies to revision r0p0 and r1p0 of A78.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_1688305_wa
/* Compare x0 against revision r1p0 */
mov x17, x30
bl check_errata_1688305
cbz x0, 1f
mrs x1, CORTEX_A78_ACTLR2_EL1
orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
msr CORTEX_A78_ACTLR2_EL1, x1
isb
1:
ret x17
endfunc errata_a78_1688305_wa
workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305
sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1
workaround_reset_end cortex_a78, ERRATUM(1688305)
func check_errata_1688305
/* Applies to r0p0 and r1p0 */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1688305
check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0)
/* --------------------------------------------------
* Errata Workaround for Cortex A78 Errata #1941498.
* This applies to revisions r0p0, r1p0, and r1p1.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_1941498_wa
/* Compare x0 against revision <= r1p1 */
mov x17, x30
bl check_errata_1941498
cbz x0, 1f
workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534
sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2
workaround_reset_end cortex_a78, ERRATUM(1821534)
/* Set bit 8 in ECTLR_EL1 */
mrs x1, CORTEX_A78_CPUECTLR_EL1
orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
msr CORTEX_A78_CPUECTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a78_1941498_wa
check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0)
func check_errata_1941498
/* Check for revision <= r1p1, might need to be updated later. */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_1941498
workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498
sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8
workaround_reset_end cortex_a78, ERRATUM(1941498)
/* --------------------------------------------------
* Errata Workaround for A78 Erratum 1951500.
* This applies to revisions r1p0 and r1p1 of A78.
* The issue also exists in r0p0 but there is no fix
* in that revision.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_1951500_wa
/* Compare x0 against revisions r1p0 - r1p1 */
mov x17, x30
bl check_errata_1951500
cbz x0, 1f
check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1)
workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500
msr S3_6_c15_c8_0, xzr
ldr x0, =0x10E3900002
msr S3_6_c15_c8_2, x0
@ -120,60 +68,11 @@ func errata_a78_1951500_wa
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
workaround_reset_end cortex_a78, ERRATUM(1951500)
isb
1:
ret x17
endfunc errata_a78_1951500_wa
func check_errata_1951500
/* Applies to revisions r1p0 and r1p1. */
mov x1, #CPU_REV(1, 0)
mov x2, #CPU_REV(1, 1)
b cpu_rev_var_range
endfunc check_errata_1951500
/* --------------------------------------------------
* Errata Workaround for Cortex A78 Errata #1821534.
* This applies to revisions r0p0 and r1p0.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_1821534_wa
/* Check revision. */
mov x17, x30
bl check_errata_1821534
cbz x0, 1f
/* Set bit 2 in ACTLR2_EL1 */
mrs x1, CORTEX_A78_ACTLR2_EL1
orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
msr CORTEX_A78_ACTLR2_EL1, x1
isb
1:
ret x17
endfunc errata_a78_1821534_wa
func check_errata_1821534
/* Applies to r0p0 and r1p0 */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1821534
/* --------------------------------------------------
* Errata Workaround for Cortex A78 Errata 1952683.
* This applies to revision r0p0.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_1952683_wa
/* Check revision. */
mov x17, x30
bl check_errata_1952683
cbz x0, 1f
check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1)
workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683
ldr x0,=0x5
msr S3_6_c15_c8_0,x0
ldr x0,=0xEEE10A10
@ -194,61 +93,21 @@ func errata_a78_1952683_wa
msr S3_6_c15_c8_3,x0
ldr x0,=0x40000080023ff
msr S3_6_c15_c8_1,x0
isb
1:
ret x17
endfunc errata_a78_1952683_wa
workaround_reset_end cortex_a78, ERRATUM(1952683)
func check_errata_1952683
/* Applies to r0p0 only */
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_1952683
/* --------------------------------------------------
* Errata Workaround for Cortex A78 Errata 2132060.
* This applies to revisions r0p0, r1p0, r1p1, and r1p2.
* It is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* --------------------------------------------------
*/
func errata_a78_2132060_wa
/* Check revision. */
mov x17, x30
bl check_errata_2132060
cbz x0, 1f
check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0)
workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060
/* Apply the workaround. */
mrs x1, CORTEX_A78_CPUECTLR_EL1
mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
msr CORTEX_A78_CPUECTLR_EL1, x1
1:
ret x17
endfunc errata_a78_2132060_wa
workaround_reset_end cortex_a78, ERRATUM(2132060)
func check_errata_2132060
/* Applies to r0p0, r0p1, r1p1, and r1p2 */
mov x1, #0x12
b cpu_rev_var_ls
endfunc check_errata_2132060
/* --------------------------------------------------------------------
* Errata Workaround for A78 Erratum 2242635.
* This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78
* processor and is still open.
* The issue also exists in r0p0 but there is no fix in that revision.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------------------------
*/
func errata_a78_2242635_wa
/* Compare x0 against revisions r1p0 - r1p2 */
mov x17, x30
bl check_errata_2242635
cbz x0, 1f
check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2)
workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635
ldr x0, =0x5
msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0x10F600E000
@ -257,242 +116,64 @@ func errata_a78_2242635_wa
msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
workaround_reset_end cortex_a78, ERRATUM(2242635)
isb
1:
ret x17
endfunc errata_a78_2242635_wa
check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2)
func check_errata_2242635
/* Applies to revisions r1p0 through r1p2. */
mov x1, #CPU_REV(1, 0)
mov x2, #CPU_REV(1, 2)
b cpu_rev_var_range
endfunc check_errata_2242635
workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745
sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0)
workaround_reset_end cortex_a78, ERRATUM(2376745)
/* --------------------------------------------------
* Errata Workaround for Cortex A78 Errata 2376745.
* This applies to revisions r0p0, r1p0, r1p1, and r1p2.
* It is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* --------------------------------------------------
*/
func errata_a78_2376745_wa
/* Check revision. */
mov x17, x30
bl check_errata_2376745
cbz x0, 1f
check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2)
/* Apply the workaround. */
mrs x1, CORTEX_A78_ACTLR2_EL1
orr x1, x1, #BIT(0)
msr CORTEX_A78_ACTLR2_EL1, x1
1:
ret x17
endfunc errata_a78_2376745_wa
workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406
sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40)
workaround_reset_end cortex_a78, ERRATUM(2395406)
func check_errata_2376745
/* Applies to r0p0, r0p1, r1p1, and r1p2 */
mov x1, #CPU_REV(1, 2)
b cpu_rev_var_ls
endfunc check_errata_2376745
/* --------------------------------------------------
* Errata Workaround for Cortex A78 Errata 2395406.
* This applies to revisions r0p0, r1p0, r1p1, and r1p2.
* It is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* --------------------------------------------------
*/
func errata_a78_2395406_wa
/* Check revision. */
mov x17, x30
bl check_errata_2395406
cbz x0, 1f
/* Apply the workaround. */
mrs x1, CORTEX_A78_ACTLR2_EL1
orr x1, x1, #BIT(40)
msr CORTEX_A78_ACTLR2_EL1, x1
1:
ret x17
endfunc errata_a78_2395406_wa
func check_errata_2395406
/* Applies to r0p0, r0p1, r1p1, and r1p2 */
mov x1, #CPU_REV(1, 2)
b cpu_rev_var_ls
endfunc check_errata_2395406
/* ----------------------------------------------------
* Errata Workaround for Cortex A78 Errata 2742426.
* This applies to revisions r0p0, r1p0, r1p1 and r1p2.
* It is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* ----------------------------------------------------
*/
func errata_a78_2742426_wa
/* Check revision. */
mov x17, x30
bl check_errata_2742426
cbz x0, 1f
check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2)
workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426
/* Apply the workaround */
mrs x1, CORTEX_A78_ACTLR5_EL1
bic x1, x1, #BIT(56)
orr x1, x1, #BIT(55)
msr CORTEX_A78_ACTLR5_EL1, x1
workaround_reset_end cortex_a78, ERRATUM(2742426)
1:
ret x17
endfunc errata_a78_2742426_wa
func check_errata_2742426
/* Applies to r0p0, r1p0, r1p1, r1p2 */
mov x1, #CPU_REV(1, 2)
b cpu_rev_var_ls
endfunc check_errata_2742426
/* ----------------------------------------------------
* Errata Workaround for Cortex-A78 Errata 2772019
* This applies to revisions <= r1p2 and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ----------------------------------------------------
*/
func errata_a78_2772019_wa
mov x17, x30
bl check_errata_2772019
cbz x0, 1f
check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2)
workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
/* dsb before isb of power down sequence */
dsb sy
1:
ret x17
endfunc errata_a78_2772019_wa
workaround_runtime_end cortex_a78, ERRATUM(2772019)
func check_errata_2772019
/* Applies to all revisions <= r1p2 */
mov x1, #0x12
b cpu_rev_var_ls
endfunc check_errata_2772019
check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2)
/* ----------------------------------------------------
* Errata Workaround for Cortex A78 Errata 2779479.
* This applies to revisions r0p0, r1p0, r1p1, and r1p2.
* It is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* ----------------------------------------------------
*/
func errata_a78_2779479_wa
/* Check revision. */
mov x17, x30
bl check_errata_2779479
cbz x0, 1f
workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479
sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47)
workaround_reset_end cortex_a78, ERRATUM(2779479)
/* Apply the workaround */
mrs x1, CORTEX_A78_ACTLR3_EL1
orr x1, x1, #BIT(47)
msr CORTEX_A78_ACTLR3_EL1, x1
check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2)
1:
ret x17
endfunc errata_a78_2779479_wa
func check_errata_2779479
/* Applies to r0p0, r1p0, r1p1, r1p2 */
mov x1, #CPU_REV(1, 2)
b cpu_rev_var_ls
endfunc check_errata_2779479
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2022_23960
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A78
* -------------------------------------------------
workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
* The Cortex-X1 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
func cortex_a78_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
override_vector_table wa_cve_vbar_cortex_a78
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_a78, CVE(2022, 23960)
#if ERRATA_A78_1688305
mov x0, x18
bl errata_a78_1688305_wa
#endif
#if ERRATA_A78_1941498
mov x0, x18
bl errata_a78_1941498_wa
#endif
#if ERRATA_A78_1951500
mov x0, x18
bl errata_a78_1951500_wa
#endif
#if ERRATA_A78_1821534
mov x0, x18
bl errata_a78_1821534_wa
#endif
#if ERRATA_A78_1952683
mov x0, x18
bl errata_a78_1952683_wa
#endif
#if ERRATA_A78_2132060
mov x0, x18
bl errata_a78_2132060_wa
#endif
#if ERRATA_A78_2242635
mov x0, x18
bl errata_a78_2242635_wa
#endif
#if ERRATA_A78_2376745
mov x0, x18
bl errata_a78_2376745_wa
#endif
#if ERRATA_A78_2395406
mov x0, x18
bl errata_a78_2395406_wa
#endif
#if ERRATA_A78_2742426
mov x0, x18
bl errata_a78_2742426_wa
#endif
#if ERRATA_A78_2779479
mov x0, x18
bl errata_a78_2779479_wa
#endif
check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
cpu_reset_func_start cortex_a78
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el3, x0
sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
mrs x0, actlr_el2
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el2, x0
sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
/* Enable group0 counters */
mov x0, #CORTEX_A78_AMU_GROUP0_MASK
@ -502,74 +183,22 @@ func cortex_a78_reset_func
mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
#endif
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Cortex-A78 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_a78
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb
ret x19
endfunc cortex_a78_reset_func
cpu_reset_func_end cortex_a78
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_a78_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
msr CORTEX_A78_CPUPWRCTLR_EL1, x0
#if ERRATA_A78_2772019
mov x15, x30
bl cpu_get_rev_var
bl errata_a78_2772019_wa
mov x30, x15
#endif /* ERRATA_A78_2772019 */
sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
isb
ret
endfunc cortex_a78_core_pwr_dwn
/*
* Errata printing function for cortex_a78. Must follow AAPCS.
*/
#if REPORT_ERRATA
func cortex_a78_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A78_1688305, cortex_a78, 1688305
report_errata ERRATA_A78_1941498, cortex_a78, 1941498
report_errata ERRATA_A78_1951500, cortex_a78, 1951500
report_errata ERRATA_A78_1821534, cortex_a78, 1821534
report_errata ERRATA_A78_1952683, cortex_a78, 1952683
report_errata ERRATA_A78_2132060, cortex_a78, 2132060
report_errata ERRATA_A78_2242635, cortex_a78, 2242635
report_errata ERRATA_A78_2376745, cortex_a78, 2376745
report_errata ERRATA_A78_2395406, cortex_a78, 2395406
report_errata ERRATA_A78_2742426, cortex_a78, 2742426
report_errata ERRATA_A78_2772019, cortex_a78, 2772019
report_errata ERRATA_A78_2779479, cortex_a78, 2779479
report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a78_errata_report
#endif
errata_report_shim cortex_a78
/* ---------------------------------------------
* This function provides cortex_a78 specific

361
lib/cpus/aarch64/cortex_a78c.S
View file

@ -17,174 +17,37 @@
#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* --------------------------------------------------
* Errata Workaround for A78C Erratum 1827430.
* This applies to revision r0p0 of the Cortex A78C
* processor and is fixed in r0p1.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78c_1827430_wa
mov x17, x30
bl check_errata_1827430
cbz x0, 1f
/* Disable allocation of splintered pages in the L2 TLB */
mrs x1, CORTEX_A78C_CPUECTLR_EL1
orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
msr CORTEX_A78C_CPUECTLR_EL1, x1
1:
ret x17
endfunc errata_a78c_1827430_wa
func check_errata_1827430
/* Applies to revision r0p0 only */
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_1827430
/* --------------------------------------------------
* Errata Workaround for A78C Erratum 1827440.
* This applies to revision r0p0 of the Cortex A78C
* processor and is fixed in r0p1.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78c_1827440_wa
mov x17, x30
bl check_errata_1827440
cbz x0, 1f
/* Force Atomic Store to WB memory be done in L1 data cache */
mrs x1, CORTEX_A78C_CPUACTLR2_EL1
orr x1, x1, #BIT(2)
msr CORTEX_A78C_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_a78c_1827440_wa
func check_errata_1827440
/* Applies to revision r0p0 only */
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_1827440
/* --------------------------------------------------
* Errata Workaround for Cortex A78C Erratum 2376749.
* This applies to revision r0p1 and r0p2 of the A78C
* and is currently open. It is a Cat B erratum.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x4, x17
* --------------------------------------------------
*/
func errata_a78c_2376749_wa
/* Check revision */
mov x17, x30
bl check_errata_2376749
cbz x0, 1f
/* Set CPUACTLR2_EL1[0] to 1. */
mrs x1, CORTEX_A78C_CPUACTLR2_EL1
orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0
msr CORTEX_A78C_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_a78c_2376749_wa
func check_errata_2376749
/* Applies to r0p1 and r0p2*/
mov x1, #0x01
mov x2, #0x02
b cpu_rev_var_range
endfunc check_errata_2376749
/* --------------------------------------------------
* Errata Workaround for Cortex A78C Erratum 2395411.
* This applies to revision r0p1 and r0p2 of the A78C
* and is currently open. It is a Cat B erratum.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x4, x17
* --------------------------------------------------
*/
func errata_a78c_2395411_wa
/* Check revision. */
mov x17, x30
bl check_errata_2395411
cbz x0, 1f
/* Set CPUACTRL2_EL1[40] to 1. */
mrs x1, CORTEX_A78C_CPUACTLR2_EL1
orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40
msr CORTEX_A78C_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_a78c_2395411_wa
func check_errata_2395411
/* Applies to r0p1 and r0p2 */
mov x1, #0x01
mov x2, #0x02
b cpu_rev_var_range
endfunc check_errata_2395411
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
#endif /* WORKAROUND_CVE_2022_23960 */
/* --------------------------------------------------
* Errata Workaround for A78C Erratum 2132064.
* This applies to revisions r0p1 and r0p2 of A78C
* and is still open.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78c_2132064_wa
/* Compare x0 against revisions r0p0 - r0p1 */
mov x17, x30
bl check_errata_2132064
cbz x0, 1f
workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430
/* Disable allocation of splintered pages in the L2 TLB */
sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
workaround_reset_end cortex_a78c, ERRATUM(1827430)
check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0)
workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440
/* Force Atomic Store to WB memory be done in L1 data cache */
sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2)
workaround_reset_end cortex_a78c, ERRATUM(1827440)
check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0)
workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064
/* --------------------------------------------------------
* Place the data prefetcher in the most conservative mode
* to reduce prefetches by writing the following bits to
* the value indicated: ecltr[7:6], PF_MODE = 2'b11
* --------------------------------------------------------
*/
mrs x0, CORTEX_A78C_CPUECTLR_EL1
orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6
orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7
msr CORTEX_A78C_CPUECTLR_EL1, x0
isb
1:
ret x17
endfunc errata_a78c_2132064_wa
sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7)
workaround_reset_end cortex_a78c, ERRATUM(2132064)
func check_errata_2132064
/* Applies to revisions r0p1 and r0p2. */
mov x1, #CPU_REV(0, 1)
mov x2, #CPU_REV(0, 2)
b cpu_rev_var_range
endfunc check_errata_2132064
/* ----------------------------------------------------------
* Errata Workaround for A78C Erratum 2242638.
* This applies to revisions r0p1 and r0p2 of the Cortex A78C
* processor and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ----------------------------------------------------------
*/
func errata_a78c_2242638_wa
/* Compare x0 against revisions r0p1 - r0p2 */
mov x17, x30
bl check_errata_2242638
cbz x0, 1f
check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2)
workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638
ldr x0, =0x5
msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
ldr x0, =0x10F600E000
@ -193,139 +56,51 @@ func errata_a78c_2242638_wa
msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
ldr x0, =0x80000000003FF
msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
workaround_reset_end cortex_a78c, ERRATUM(2242638)
isb
1:
ret x17
endfunc errata_a78c_2242638_wa
check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2)
func check_errata_2242638
/* Applies to revisions r0p1-r0p2. */
mov x1, #CPU_REV(0, 1)
mov x2, #CPU_REV(0, 2)
b cpu_rev_var_range
endfunc check_errata_2242638
workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749
sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0
workaround_reset_end cortex_a78c, ERRATUM(2376749)
/* ----------------------------------------------------------------
* Errata Workaround for A78C Erratum 2772121.
* This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C
* processor and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ----------------------------------------------------------------
*/
func errata_a78c_2772121_wa
mov x17, x30
bl check_errata_2772121
cbz x0, 1f
check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2)
workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411
sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40
workaround_reset_end cortex_a78c, ERRATUM(2395411)
check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
/* dsb before isb of power down sequence */
dsb sy
1:
ret x17
endfunc errata_a78c_2772121_wa
workaround_runtime_end cortex_a78c, ERRATUM(2772121)
func check_errata_2772121
/* Applies to all revisions <= r0p2 */
mov x1, #0x02
b cpu_rev_var_ls
endfunc check_errata_2772121
check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2)
/* --------------------------------------------------
* Errata Workaround for Cortex A78C Errata 2779484.
* This applies to revisions r0p1 and r0p2.
* It is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* --------------------------------------------------
*/
func errata_a78c_2779484_wa
/* Check revision. */
mov x17, x30
bl check_errata_2779484
cbz x0, 1f
workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484
sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47)
workaround_reset_end cortex_a78c, ERRATUM(2779484)
/* Apply the workaround */
mrs x1, CORTEX_A78C_ACTLR3_EL1
orr x1, x1, #BIT(47)
msr CORTEX_A78C_ACTLR3_EL1, x1
check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2)
1:
ret x17
endfunc errata_a78c_2779484_wa
check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
func check_errata_2779484
/* Applies to r0p1 and r0p2*/
mov x1, #0x01
mov x2, #0x02
b cpu_rev_var_range
endfunc check_errata_2779484
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2022_23960
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A78C
* -------------------------------------------------
*/
func cortex_a78c_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A78C_1827430
mov x0, x18
bl errata_a78c_1827430_wa
#endif
#if ERRATA_A78C_1827440
mov x0, x18
bl errata_a78c_1827440_wa
#endif
#if ERRATA_A78C_2132064
mov x0, x18
bl errata_a78c_2132064_wa
#endif
#if ERRATA_A78C_2242638
mov x0, x18
bl errata_a78c_2242638_wa
#endif
#if ERRATA_A78C_2376749
mov x0, x18
bl errata_a78c_2376749_wa
#endif
#if ERRATA_A78C_2395411
mov x0, x18
bl errata_a78c_2395411_wa
#endif
#if ERRATA_A78C_2779484
mov x0, x18
bl errata_a78c_2779484_wa
#endif
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
* The Cortex-A78c generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_a78c
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
override_vector_table wa_cve_vbar_cortex_a78c
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_a78c, CVE(2022, 23960)
isb
ret x19
endfunc cortex_a78c_reset_func
cpu_reset_func_start cortex_a78c
cpu_reset_func_end cortex_a78c
errata_report_shim cortex_a78c
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@ -336,48 +111,14 @@ func cortex_a78c_core_pwr_dwn
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
#if ERRATA_A78C_2772121
mov x15, x30
bl cpu_get_rev_var
bl errata_a78c_2772121_wa
mov x30, x15
#endif /* ERRATA_A78C_2772121 */
sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
isb
ret
endfunc cortex_a78c_core_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex A78C. Must follow AAPCS.
*/
func cortex_a78c_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430
report_errata ERRATA_A78C_1827440, cortex_a78c, 1827440
report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121
report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484
report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a78c_errata_report
#endif
/* ---------------------------------------------
* This function provides cortex_a78c specific
* register information for crash reporting.

171
lib/cpus/aarch64/cortex_x1.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Google LLC. All rights reserved.
* Copyright (c) 2022-2023, Google LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -23,175 +23,50 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1
#endif /* WORKAROUND_CVE_2022_23960 */
/* --------------------------------------------------
* Errata Workaround for X1 Erratum 1821534.
* This applies to revision r0p0 and r1p0 of X1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_x1_1821534_wa
/* Compare x0 against revision r1p0 */
mov x17, x30
bl check_errata_1821534
cbz x0, 1f
mrs x1, CORTEX_X1_ACTLR2_EL1
orr x1, x1, #BIT(2)
msr CORTEX_X1_ACTLR2_EL1, x1
isb
1:
ret x17
endfunc errata_x1_1821534_wa
workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305
sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1)
workaround_reset_end cortex_x1, ERRATUM(1688305)
func check_errata_1821534
/* Applies to r0p0 and r1p0 */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1821534
check_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0)
/* --------------------------------------------------
* Errata Workaround for X1 Erratum 1688305.
* This applies to revision r0p0 and r1p0 of X1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_x1_1688305_wa
/* Compare x0 against revision r1p0 */
mov x17, x30
bl check_errata_1688305
cbz x0, 1f
mrs x0, CORTEX_X1_ACTLR2_EL1
orr x0, x0, #BIT(1)
msr CORTEX_X1_ACTLR2_EL1, x0
isb
workaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534
sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(2)
workaround_reset_end cortex_x1, ERRATUM(1821534)
1:
ret x17
endfunc errata_x1_1688305_wa
check_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0)
func check_errata_1688305
/* Applies to r0p0 and r1p0 */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1688305
workaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429
sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(53)
workaround_reset_end cortex_x1, ERRATUM(1827429)
/* --------------------------------------------------
* Errata Workaround for X1 Erratum 1827429.
* This applies to revision r0p0 and r1p0 of X1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_x1_1827429_wa
/* Compare x0 against revision r1p0 */
mov x17, x30
bl check_errata_1827429
cbz x0, 1f
mrs x0, CORTEX_X1_CPUECTLR_EL1
orr x0, x0, #BIT(53)
msr CORTEX_X1_CPUECTLR_EL1, x0
isb
check_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0)
1:
ret x17
endfunc errata_x1_1827429_wa
check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
func check_errata_1827429
/* Applies to r0p0 and r1p0 */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1827429
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2022_23960
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-X1.
* Shall clobber: x0-x19
* -------------------------------------------------
*/
func cortex_x1_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_X1_1821534
mov x0, x18
bl errata_x1_1821534_wa
#endif
#if ERRATA_X1_1688305
mov x0, x18
bl errata_x1_1688305_wa
#endif
#if ERRATA_X1_1827429
mov x0, x18
bl errata_x1_1827429_wa
#endif
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
* The Cortex-X1 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_x1
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
override_vector_table wa_cve_vbar_cortex_x1
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_x1, CVE(2022, 23960)
isb
ret x19
endfunc cortex_x1_reset_func
cpu_reset_func_start cortex_x1
cpu_reset_func_end cortex_x1
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_x1_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
mrs x0, CORTEX_X1_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK
msr CORTEX_X1_CPUPWRCTLR_EL1, x0
sysreg_bit_set CORTEX_X1_CPUPWRCTLR_EL1, CORTEX_X1_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_x1_core_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex X1. Must follow AAPCS.
*/
func cortex_x1_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_X1_1821534, cortex_x1, 1821534
report_errata ERRATA_X1_1688305, cortex_x1, 1688305
report_errata ERRATA_X1_1827429, cortex_x1, 1827429
report_errata WORKAROUND_CVE_2022_23960, cortex_x1, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_x1_errata_report
#endif
errata_report_shim cortex_x1
/* ---------------------------------------------
* This function provides Cortex X1 specific