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Merge changes from topic "jc/errata_refactor" into integration
* changes: refactor(cpus): convert Cortex-A72 to use cpu helpers refactor(cpus): convert the Cortex-A72 to use the errata framework refactor(cpus): reorder Cortex-A72 errata by ascending order
This commit is contained in:
Lauren Wehrmeister
TrustedFirmware Code Review
commit
231305ec0f
1 changed files with 65 additions and 136 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -47,9 +47,7 @@ endfunc cortex_a72_disable_l2_prefetch
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* ---------------------------------------------
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*/
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func cortex_a72_disable_hw_prefetcher
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mrs x0, CORTEX_A72_CPUACTLR_EL1
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orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
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msr CORTEX_A72_CPUACTLR_EL1, x0
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sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
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isb
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dsb ish
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ret
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@ -60,9 +58,7 @@ endfunc cortex_a72_disable_hw_prefetcher
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* ---------------------------------------------
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*/
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func cortex_a72_disable_smp
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mrs x0, CORTEX_A72_ECTLR_EL1
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bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
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msr CORTEX_A72_ECTLR_EL1, x0
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sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
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ret
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endfunc cortex_a72_disable_smp
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@ -78,31 +74,33 @@ func cortex_a72_disable_ext_debug
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ret
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endfunc cortex_a72_disable_ext_debug
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/* --------------------------------------------------
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* Errata Workaround for Cortex A72 Errata #859971.
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* This applies only to revision <= r0p3 of Cortex A72.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber:
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* --------------------------------------------------
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*/
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func errata_a72_859971_wa
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mov x17,x30
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bl check_errata_859971
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cbz x0, 1f
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mrs x1, CORTEX_A72_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
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msr CORTEX_A72_CPUACTLR_EL1, x1
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func check_smccc_arch_workaround_3
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cpu_check_csv2 x0, 1f
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mov x0, #ERRATA_APPLIES
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ret
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1:
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ret x17
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endfunc errata_a72_859971_wa
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_smccc_arch_workaround_3
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func check_errata_859971
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mov x1, #0x03
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b cpu_rev_var_ls
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endfunc check_errata_859971
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workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971
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sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
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workaround_reset_end cortex_a72, ERRATUM(859971)
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func check_errata_cve_2017_5715
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check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3)
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367, NO_APPLY_AT_RESET
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workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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#if IMAGE_BL31
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override_vector_table wa_cve_2017_5715_mmu_vbar
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#endif
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workaround_reset_end cortex_a72, CVE(2017, 5715)
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check_erratum_custom_start cortex_a72, CVE(2017, 5715)
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cpu_check_csv2 x0, 1f
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#if WORKAROUND_CVE_2017_5715
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mov x0, #ERRATA_APPLIES
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@ -113,104 +111,58 @@ func check_errata_cve_2017_5715
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_errata_cve_2017_5715
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check_erratum_custom_end cortex_a72, CVE(2017, 5715)
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func check_errata_cve_2018_3639
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#if WORKAROUND_CVE_2018_3639
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2018_3639
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workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
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isb
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dsb sy
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workaround_reset_end cortex_a72, CVE(2018, 3639)
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check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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/* --------------------------------------------------
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* Errata workaround for Cortex A72 Errata #1319367.
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* This applies to all revisions of Cortex A72.
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* --------------------------------------------------
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*/
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func check_errata_1319367
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#if ERRATA_A72_1319367
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_1319367
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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func check_smccc_arch_workaround_3
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cpu_check_csv2 x0, 1f
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mov x0, #ERRATA_APPLIES
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ret
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_smccc_arch_workaround_3
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A72.
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* -------------------------------------------------
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*/
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func cortex_a72_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A72_859971
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mov x0, x18
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bl errata_a72_859971_wa
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#endif
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#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
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cpu_check_csv2 x0, 1f
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adr x0, wa_cve_2017_5715_mmu_vbar
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msr vbar_el3, x0
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/* isb will be performed before returning from this function */
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/* Skip CVE_2022_23960 mitigation if cve_2017_5715 mitigation applied */
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b 2f
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1:
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#if WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/* Skip installing vector table again if already done for CVE(2017, 5715) */
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/*
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* The Cortex-A72 generic vectors are overridden to apply the
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* mitigation on exception entry from lower ELs for revisions >= r1p0
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* mitigation on exception entry from lower ELs for revisions >= r1p0
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* which has CSV2 implemented.
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*/
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adr x0, wa_cve_vbar_cortex_a72
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mrs x1, vbar_el3
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cmp x0, x1
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b.eq 1f
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msr vbar_el3, x0
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1:
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a72, CVE(2022, 23960)
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/* isb will be performed before returning from this function */
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check_erratum_custom_start cortex_a72, CVE(2022, 23960)
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#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
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cpu_check_csv2 x0, 1f
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mov x0, #ERRATA_APPLIES
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ret
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1:
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif /* WORKAROUND_CVE_2022_23960 */
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2:
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#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
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ret
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#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
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mov x0, #ERRATA_MISSING
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ret
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check_erratum_custom_end cortex_a72, CVE(2022, 23960)
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#if WORKAROUND_CVE_2018_3639
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mrs x0, CORTEX_A72_CPUACTLR_EL1
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orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
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msr CORTEX_A72_CPUACTLR_EL1, x0
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isb
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dsb sy
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#endif
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cpu_reset_func_start cortex_a72
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A72_ECTLR_EL1
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orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
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msr CORTEX_A72_ECTLR_EL1, x0
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isb
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ret x19
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endfunc cortex_a72_reset_func
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sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
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cpu_reset_func_end cortex_a72
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A72.
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@ -319,30 +271,7 @@ func cortex_a72_cluster_pwr_dwn
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A72. Must follow AAPCS.
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*/
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func cortex_a72_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A72_859971, cortex_a72, 859971
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report_errata ERRATA_A72_1319367, cortex_a72, 1319367
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report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715
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report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639
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report_errata WORKAROUND_CVE_2022_23960, cortex_a72, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a72_errata_report
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#endif
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errata_report_shim cortex_a72
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/* ---------------------------------------------
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* This function provides cortex_a72 specific
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@ -367,7 +296,7 @@ endfunc cortex_a72_cpu_reg_dump
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declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \
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cortex_a72_reset_func, \
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check_errata_cve_2017_5715, \
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check_erratum_cortex_a72_5715, \
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CPU_NO_EXTRA2_FUNC, \
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check_smccc_arch_workaround_3, \
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cortex_a72_core_pwr_dwn, \
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