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refactor(cpus): reorder Cortex-A73 errata by ascending order

Browse source 
Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.

Change-Id: I70b05cc366c3b6d07a63edd88d23a52dd3d019c1
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
This commit is contained in:
Sona Mathew 2023-06-19 15:37:09 -05:00
parent 5c7d12cbd9
commit e2da5e0ed7
1 changed files with 45 additions and 44 deletions
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89
lib/cpus/aarch64/cortex_a73.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -35,6 +35,11 @@ func cortex_a73_disable_smp
ret
endfunc cortex_a73_disable_smp
func check_smccc_arch_workaround_3
mov x0, #ERRATA_APPLIES
ret
endfunc check_smccc_arch_workaround_3
/* ---------------------------------------------------
* Errata Workaround for Cortex A73 Errata #852427.
* This applies only to revision r0p0 of Cortex A73.
@ -91,6 +96,45 @@ func check_errata_855423
b cpu_rev_var_ls
endfunc check_errata_855423
func check_errata_cve_2017_5715
cpu_check_csv2 x0, 1f
#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
endfunc check_errata_cve_2017_5715
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2018_3639
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
cpu_check_csv2 x0, 1f
mov x0, #ERRATA_APPLIES
ret
1:
# if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
# else
mov x0, #ERRATA_MISSING
# endif /* WORKAROUND_CVE_2022_23960 */
ret
#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
mov x0, #ERRATA_MISSING
ret
endfunc check_errata_cve_2022_23960
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A73.
* -------------------------------------------------
@ -207,49 +251,6 @@ func cortex_a73_cluster_pwr_dwn
b cortex_a73_disable_smp
endfunc cortex_a73_cluster_pwr_dwn
func check_errata_cve_2017_5715
cpu_check_csv2 x0, 1f
#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
endfunc check_errata_cve_2017_5715
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2018_3639
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
cpu_check_csv2 x0, 1f
mov x0, #ERRATA_APPLIES
ret
1:
# if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
# else
mov x0, #ERRATA_MISSING
# endif /* WORKAROUND_CVE_2022_23960 */
ret
#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
mov x0, #ERRATA_MISSING
ret
endfunc check_errata_cve_2022_23960
func check_smccc_arch_workaround_3
mov x0, #ERRATA_APPLIES
ret
endfunc check_smccc_arch_workaround_3
#if REPORT_ERRATA
/*