Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 01:24:27 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(cpus): workaround for Neoverse N2 erratum 2779511

Browse source 
Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CPUACTLR3_EL1

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iaa0e30de8473ecb1df1fcca3a45904aac2e419b3
This commit is contained in:
Arvind Ram Prakash 2023-07-17 14:46:14 -05:00
parent 7e030b3763
commit 12d28067c9
5 changed files with 23 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
docs/design/cpu-specific-build-macros.rst
View file

@ -654,6 +654,10 @@ For Neoverse N2, the following errata build flags are defined :
interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
It is fixed in r0p3.
- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
in r0p3.
For Cortex-X2, the following errata build flags are defined :
- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2

6
include/lib/cpus/aarch64/neoverse_n2.h
View file

@ -42,6 +42,12 @@
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
/*******************************************************************************
* CPU Auxiliary Control register 3 specific definitions.
******************************************************************************/
#define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2
#define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.
******************************************************************************/

7
lib/cpus/aarch64/neoverse_n2.S
View file

@ -181,6 +181,13 @@ workaround_runtime_end neoverse_n2, ERRATUM(2743089)
check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2)
workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511
/* Set bit 47 in ACTLR3_EL1 */
sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47
workaround_reset_end neoverse_n2, ERRATUM(2779511)
check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2)
workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*

4
lib/cpus/cpu-ops.mk
View file

@ -676,6 +676,10 @@ CPU_FLAG_LIST += ERRATA_N2_2743014
# applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
CPU_FLAG_LIST += ERRATA_N2_2743089
# Flag to apply erratum 2779511 workaround during reset. This erratum applies
# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
CPU_FLAG_LIST += ERRATA_N2_2779511
# Flag to apply erratum 2002765 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_2002765

3
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -348,7 +348,8 @@ struct em_cpu_list cpu_list[] = {
ERRATA_NON_ARM_INTERCONNECT},
[14] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
[15] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
[16 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[16] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
[17 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N2_H_INC */