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refactor(cpus): convert the Cortex-A55 to use the errata framework

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Testing:
   - Manual comparison of disassembly with and without conversion.
   - Using the test script in gerrit - 19136
   - Building with errata and stepping through from ArmDS and running tftf.

Change-Id: I2ff16be8bb568e37477edbbd7551877cbbde4c60
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2023-06-15 15:44:42 -05:00
parent 91ba1a5edf
commit 1de3c3a95b
1 changed files with 45 additions and 228 deletions

273
lib/cpus/aarch64/cortex_a55.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -18,63 +18,43 @@
.globl cortex_a55_reset_func
.globl cortex_a55_core_pwr_dwn
/* --------------------------------------------------
* Errata Workaround for Cortex A55 Errata #768277.
* This applies only to revision r0p0 of Cortex A55.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a55_768277_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_768277
cbz x0, 1f
/* ERRATA_DSU_798953:
* The errata is defined in dsu_helpers.S but applies to cortex_a55
* as well. Henceforth creating symbolic names to the already existing errata
* workaround functions to get them registered under the Errata Framework.
*/
.equ check_erratum_cortex_a55_798953, check_errata_dsu_798953
.equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa
add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
/* ERRATA_DSU_936184:
* The errata is defined in dsu_helpers.S but applies to cortex_a55
* as well. Henceforth creating symbolic names to the already existing errata
* workaround functions to get them registered under the Errata Framework.
*/
.equ check_erratum_cortex_a55_936184, check_errata_dsu_936184
.equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa
add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_768277_wa
workaround_reset_end cortex_a55, ERRATUM(768277)
func check_errata_768277
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_768277
check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0)
/* ------------------------------------------------------------------
* Errata Workaround for Cortex A55 Errata #778703.
* This applies only to revision r0p0 of Cortex A55 where L2 cache is
* not configured.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ------------------------------------------------------------------
*/
func errata_a55_778703_wa
/*
* Compare x0 against revision r0p0 and check that no private L2 cache
* is configured
*/
mov x17, x30
bl check_errata_778703
cbz x0, 1f
workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703
mrs x1, CORTEX_A55_CPUECTLR_EL1
orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL
msr CORTEX_A55_CPUECTLR_EL1, x1
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_778703_wa
workaround_reset_end cortex_a55, ERRATUM(778703)
func check_errata_778703
check_erratum_custom_start cortex_a55, ERRATUM(778703)
mov x16, x30
mov x1, #0x00
bl cpu_rev_var_ls
@ -87,111 +67,33 @@ func check_errata_778703
mov x2, #ERRATA_NOT_APPLIES
csel x0, x0, x2, eq
ret x16
endfunc check_errata_778703
check_erratum_custom_end cortex_a55, ERRATUM(778703)
/* --------------------------------------------------
* Errata Workaround for Cortex A55 Errata #798797.
* This applies only to revision r0p0 of Cortex A55.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a55_798797_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_798797
cbz x0, 1f
workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_798797_wa
workaround_reset_end cortex_a55, ERRATUM(798797)
func check_errata_798797
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_798797
check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
/* --------------------------------------------------------------------
* Errata Workaround for Cortex A55 Errata #846532.
* This applies only to revisions <= r0p1 of Cortex A55.
* Disabling dual-issue has a small impact on performance. Disabling a
* power optimization feature is an alternate workaround with no impact
* on performance but with an increase in power consumption (see errata
* notice).
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------------------------
*/
func errata_a55_846532_wa
/*
* Compare x0 against revision r0p1
*/
mov x17, x30
bl check_errata_846532
cbz x0, 1f
workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_846532_wa
workaround_reset_end cortex_a55, ERRATUM(846532)
func check_errata_846532
mov x1, #0x01
b cpu_rev_var_ls
endfunc check_errata_846532
check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1)
/* -----------------------------------------------------
* Errata Workaround for Cortex A55 Errata #903758.
* This applies only to revisions <= r0p1 of Cortex A55.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* -----------------------------------------------------
*/
func errata_a55_903758_wa
/*
* Compare x0 against revision r0p1
*/
mov x17, x30
bl check_errata_903758
cbz x0, 1f
workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758
mrs x1, CORTEX_A55_CPUACTLR_EL1
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
msr CORTEX_A55_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a55_903758_wa
workaround_reset_end cortex_a55, ERRATUM(903758)
func check_errata_903758
mov x1, #0x01
b cpu_rev_var_ls
endfunc check_errata_903758
check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
/* -----------------------------------------------------
* Errata Workaround for Cortex A55 Errata #1221012.
* This applies only to revisions <= r1p0 of Cortex A55.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* -----------------------------------------------------
*/
func errata_a55_1221012_wa
/*
* Compare x0 against revision r1p0
*/
mov x17, x30
bl check_errata_1221012
cbz x0, 1f
workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
mov x0, #0x0020
movk x0, #0x0850, lsl #16
msr CPUPOR_EL3, x0
@ -214,76 +116,19 @@ func errata_a55_1221012_wa
mov x0, #0x03fd
movk x0, #0x0110, lsl #16
msr CPUPCR_EL3, x0
isb
1:
ret x17
endfunc errata_a55_1221012_wa
workaround_reset_end cortex_a55, ERRATUM(1221012)
func check_errata_1221012
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1221012
check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0)
/* --------------------------------------------------
* Errata workaround for Cortex A55 Errata #1530923.
* This applies to all revisions of Cortex A55.
* --------------------------------------------------
*/
func check_errata_1530923
#if ERRATA_A55_1530923
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_1530923
check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923
func cortex_a55_reset_func
mov x19, x30
/* erratum has no workaround in the cpu. Generic code must take care */
add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET
#if ERRATA_DSU_798953
bl errata_dsu_798953_wa
#endif
cpu_reset_func_start cortex_a55
cpu_reset_func_end cortex_a55
#if ERRATA_DSU_936184
bl errata_dsu_936184_wa
#endif
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A55_768277
mov x0, x18
bl errata_a55_768277_wa
#endif
#if ERRATA_A55_778703
mov x0, x18
bl errata_a55_778703_wa
#endif
#if ERRATA_A55_798797
mov x0, x18
bl errata_a55_798797_wa
#endif
#if ERRATA_A55_846532
mov x0, x18
bl errata_a55_846532_wa
#endif
#if ERRATA_A55_903758
mov x0, x18
bl errata_a55_903758_wa
#endif
#if ERRATA_A55_1221012
mov x0, x18
bl errata_a55_1221012_wa
#endif
ret x19
endfunc cortex_a55_reset_func
errata_report_shim cortex_a55
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@ -301,34 +146,6 @@ func cortex_a55_core_pwr_dwn
ret
endfunc cortex_a55_core_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex A55. Must follow AAPCS & can use stack.
*/
func cortex_a55_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision variant information is at x8, where
* "report_errata" is expecting it and it doesn't corrupt it.
*/
report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953
report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
report_errata ERRATA_A55_768277, cortex_a55, 768277
report_errata ERRATA_A55_778703, cortex_a55, 778703
report_errata ERRATA_A55_798797, cortex_a55, 798797
report_errata ERRATA_A55_846532, cortex_a55, 846532
report_errata ERRATA_A55_903758, cortex_a55, 903758
report_errata ERRATA_A55_1221012, cortex_a55, 1221012
report_errata ERRATA_A55_1530923, cortex_a55, 1530923
ldp x8, x30, [sp], #16
ret
endfunc cortex_a55_errata_report
#endif
/* ---------------------------------------------
* This function provides cortex_a55 specific
* register information for crash reporting.