mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-15 09:04:17 +00:00
Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration
* changes: plat: marvell: armada: a8k: add OP-TEE OS MMU tables drivers: marvell: add support for mapping the entire LLC to SRAM plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms plat: marvell: armada: reduce memory size reserved for FIP image plat: marvell: armada: platform definitions cleanup plat: marvell: armada: a8k: check CCU window state before loading MSS BL2 drivers: marvell: add CCU driver API for window state checking drivers: marvell: align and extend llc macros plat: marvell: a8k: move address config of cp1/2 to BL2 plat: marvell: armada: re-enable BL32_BASE definition plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer marvell: comphy: initialize common phy selector for AP mode marvell: comphy: update rx_training procedure plat: marvell: armada: configure amb for all CPs plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
edd8188d32
44 changed files with 329 additions and 197 deletions
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@ -77,6 +77,13 @@ There are several build options:
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Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``).
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- LLC_SRAM
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Flag defining the LLC (L3) cache SRAM support. The feature is
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disabled by default (``LLC_ENABLE=0``).
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When LLC SRAM is enabled, the secure payload (BL32) is loaded into this
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SRAM area instead of the DRAM.
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- MARVELL_SECURE_BOOT
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Build trusted(=1)/non trusted(=0) image, default is non trusted.
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@ -31,19 +31,19 @@ void llc_cache_sync(int ap_index)
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void llc_flush_all(int ap_index)
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{
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mmio_write_32(L2X0_CLEAN_INV_WAY(ap_index), LLC_WAY_MASK);
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mmio_write_32(LLC_CLEAN_INV_WAY(ap_index), LLC_ALL_WAYS_MASK);
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llc_cache_sync(ap_index);
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}
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void llc_clean_all(int ap_index)
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{
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mmio_write_32(L2X0_CLEAN_WAY(ap_index), LLC_WAY_MASK);
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mmio_write_32(LLC_CLEAN_WAY(ap_index), LLC_ALL_WAYS_MASK);
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llc_cache_sync(ap_index);
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}
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void llc_inv_all(int ap_index)
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{
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mmio_write_32(L2X0_INV_WAY(ap_index), LLC_WAY_MASK);
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mmio_write_32(LLC_INV_WAY(ap_index), LLC_ALL_WAYS_MASK);
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llc_cache_sync(ap_index);
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}
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@ -109,3 +109,41 @@ void llc_runtime_enable(int ap_index)
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reg |= (0x1 << CCU_SET_POC_OFFSET);
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mmio_write_32(CCU_HTC_CR(ap_index), reg);
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}
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#if LLC_SRAM
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void llc_sram_enable(int ap_index)
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{
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uint32_t tc, way;
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uint32_t way_addr;
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/* Lockdown all available ways for all traffic classes */
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for (tc = 0; tc < LLC_TC_NUM; tc++)
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mmio_write_32(LLC_TCN_LOCK(ap_index, tc), LLC_WAY_MASK);
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/* Clear the high bits of SRAM address */
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mmio_write_32(LLC_BANKED_MNT_AHR(ap_index), 0);
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way_addr = PLAT_MARVELL_TRUSTED_RAM_BASE;
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for (way = 0; way < LLC_WAYS; way++) {
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/* Trigger allocation block command */
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mmio_write_32(LLC_BLK_ALOC(ap_index),
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LLC_BLK_ALOC_BASE_ADDR(way_addr) |
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LLC_BLK_ALOC_WAY_DATA_CLR |
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LLC_BLK_ALOC_WAY_ID(way));
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way_addr += LLC_WAY_SIZE;
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}
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llc_enable(ap_index, 1);
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}
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void llc_sram_disable(int ap_index)
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{
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uint32_t tc;
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/* Disable the line lockings */
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for (tc = 0; tc < LLC_TC_NUM; tc++)
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mmio_write_32(LLC_TCN_LOCK(ap_index, tc), 0);
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/* Invalidate all ways */
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llc_inv_all(ap_index);
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}
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#endif /* LLC_SRAM */
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@ -54,8 +54,8 @@ static void dump_ccu(int ap_index)
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win_id));
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start = ((uint64_t)alr << ADDRESS_SHIFT);
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end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
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printf("\tccu %02x 0x%016llx 0x%016llx\n",
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target_id, start, end);
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printf("\tccu%d %02x 0x%016llx 0x%016llx\n",
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win_id, target_id, start, end);
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}
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}
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win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index));
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@ -81,6 +81,12 @@ void ccu_win_check(struct addr_map_win *win)
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}
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}
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int ccu_is_win_enabled(int ap_index, uint32_t win_id)
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{
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return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) &
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WIN_ENABLE_BIT;
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}
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void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id)
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{
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uint32_t ccu_win_reg;
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@ -659,18 +659,32 @@
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(0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET)
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#define HPIPE_CDR_CONTROL_REG 0x418
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET 0
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#define HPIPE_CRD_MIDPOINT_PHASE_OS_MASK \
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(0x3f << HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
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#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CDR_CONTROL1_REG 0x41c
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#define HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF 12
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#define HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK \
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(0xf << HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF)
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#define HPIPE_CDR_CONTROL2_REG 0x420
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#define HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF 12
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#define HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK \
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(0xf << HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF)
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#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
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#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
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@ -749,6 +763,30 @@
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#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
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(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
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#define HPIPE_TRX0_REG 0x4cc /*in doc 0x133*4*/
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#define HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF 2
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#define HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK \
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(0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF)
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#define HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF 0
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#define HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK \
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(0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF)
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#define HPIPE_TRX_REG1 0x4d0 /*in doc 0x134*4*/
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#define HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF 3
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#define HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK \
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(0x1 << HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF)
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#define HPIPE_TRX_REG1_SUMFTAP_EN_OFF 10
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#define HPIPE_TRX_REG1_SUMFTAP_EN_MASK \
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(0x3f << HPIPE_TRX_REG1_SUMFTAP_EN_OFF)
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#define HPIPE_TRX_REG2 0x4d8 /*in doc 0x136*4*/
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#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF 11
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#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK \
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(0x1f << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF)
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#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF 7
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#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK \
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(0xf << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF)
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#define HPIPE_G1_SETTING_5_REG 0x538
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#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
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#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
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@ -209,8 +209,10 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base,
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* as SFI1/XFI1 available only for CP115.
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*/
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if ((mode == COMPHY_SGMII_MODE ||
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mode == COMPHY_HS_SGMII_MODE ||
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mode == COMPHY_SFI_MODE || mode == COMPHY_XFI_MODE)
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mode == COMPHY_HS_SGMII_MODE ||
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mode == COMPHY_SFI_MODE ||
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mode == COMPHY_XFI_MODE ||
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mode == COMPHY_AP_MODE)
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&& COMPHY_GET_ID(comphy_mode) == 1)
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reg |= COMMON_SELECTOR_COMPHY4_PORT1 <<
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comphy_offset;
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@ -2012,12 +2014,58 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
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return ret;
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}
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static void rx_pre_train(uint64_t comphy_base, uint8_t comphy_index)
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{
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uintptr_t hpipe_addr;
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uint32_t mask, data;
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hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
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comphy_index);
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debug("rx_training preparation\n\n");
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mask = HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK;
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data = (0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF);
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mask |= HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK;
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data |= (0x0 << HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF);
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reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask);
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mask = HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
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data = (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
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mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK;
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data |= (0x0 << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF);
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reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask);
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mask = HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK;
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data = (0x1 << HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF);
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reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
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mask = HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK;
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data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF);
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reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask);
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mask = HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK;
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data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF);
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reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask);
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mask = HPIPE_CRD_MIDPOINT_PHASE_OS_MASK;
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data = (0x0 << HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET);
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reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
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mask = HPIPE_TRX_REG1_SUMFTAP_EN_MASK;
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data = (0x38 << HPIPE_TRX_REG1_SUMFTAP_EN_OFF);
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mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
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data |= (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
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reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
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}
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int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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uint8_t comphy_index)
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{
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uint32_t mask, data, timeout;
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uint32_t g1_ffe_cap_sel, g1_ffe_res_sel, align90, g1_dfe_res;
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uintptr_t hpipe_addr, sd_ip_addr;
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uintptr_t hpipe_addr;
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uint8_t ap_nr, cp_nr;
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@ -2025,30 +2073,10 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
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comphy_index);
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sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
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comphy_index);
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debug_enter();
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debug("stage: RF Reset\n");
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/* Release from hard reset */
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mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
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data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
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mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
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data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
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mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
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data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
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reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
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mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
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data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
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mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
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data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
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reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
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/* Wait 50ms - until band gap and ref clock ready */
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mdelay(50);
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rx_pre_train(comphy_base, comphy_index);
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debug("Preparation for rx_training\n\n");
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@ -2068,34 +2096,10 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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data = 0 << HPIPE_DFE_RES_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
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debug("PRBS31 loppback\n\n");
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/* Configure PRBS counters */
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mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
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data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mask = HPIPE_PHY_TEST_DATA_MASK;
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data = 0xc4 << HPIPE_PHY_TEST_DATA_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
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mask = HPIPE_PHY_TEST_EN_MASK;
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data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mdelay(10);
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debug("Enable TX/RX training\n\n");
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debug("Enable RX training\n\n");
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mask = HPIPE_TRX_RX_TRAIN_EN_MASK;
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data = 0x1 << HPIPE_TRX_RX_TRAIN_EN_OFFSET;
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mask |= HPIPE_TRX_RX_ANA_IF_CLK_ENE_MASK;
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data |= 0x1 << HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET;
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mask |= HPIPE_TRX_TX_CTRL_CLK_EN_MASK;
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data |= 0x1 << HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET;
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mask |= HPIPE_TRX_UPDATE_THEN_HOLD_MASK;
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data |= 0x1 << HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET;
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mask |= HPIPE_TRX_TX_F0T_EO_BASED_MASK;
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data |= 0x1 << HPIPE_TRX_TX_F0T_EO_BASED_OFFSET;
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reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
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/* Check the result of RX training */
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@ -2180,21 +2184,9 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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data = 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
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/* Use the value from CAL_OS_PH_EXT */
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mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK;
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data = 1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG,
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data, mask);
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/* Update align90 */
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mask = HPIPE_CAL_OS_PH_EXT_MASK;
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data = align90 << HPIPE_CAL_OS_PH_EXT_OFFSET;
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reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG,
|
||||
data, mask);
|
||||
|
||||
/* Force DFE resolution (use gen table value) */
|
||||
mask = HPIPE_DFE_RES_FORCE_MASK;
|
||||
data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
|
||||
data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
|
||||
|
||||
/* 0x111-G1 DFE_Setting_4 */
|
||||
|
|
@ -2202,38 +2194,6 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
|
|||
data = g1_dfe_res << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
|
||||
|
||||
debug("PRBS31 loppback\n\n");
|
||||
|
||||
mask = HPIPE_PHY_TEST_PT_TESTMODE_MASK;
|
||||
data = 0x1 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_PHY_TEST_OOB_0_REGISTER, data, mask);
|
||||
|
||||
/* Configure PRBS counters */
|
||||
mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
|
||||
data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
|
||||
|
||||
mask = HPIPE_PHY_TEST_DATA_MASK;
|
||||
data = 0xc4 << HPIPE_PHY_TEST_DATA_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
|
||||
|
||||
mask = HPIPE_PHY_TEST_EN_MASK;
|
||||
data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
|
||||
|
||||
/* Reset PRBS error counter */
|
||||
mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
|
||||
data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
|
||||
|
||||
mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
|
||||
data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
|
||||
|
||||
mask = HPIPE_PHY_TEST_PT_TESTMODE_MASK;
|
||||
data = 0x1 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_PHY_TEST_OOB_0_REGISTER, data, mask);
|
||||
|
||||
printf("########################################################\n");
|
||||
printf("# To use trained values update the ATF sources:\n");
|
||||
printf("# plat/marvell/armada/a8k/<board_type>/board/phy-porting-layer.h ");
|
||||
|
|
@ -2252,12 +2212,6 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
|
|||
printf("};\n\n");
|
||||
printf("########################################################\n");
|
||||
|
||||
/* check */
|
||||
debug("PRBS error counter[0x%lx] 0x%x\n\n",
|
||||
hpipe_addr + HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG,
|
||||
mmio_read_32(hpipe_addr +
|
||||
HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG));
|
||||
|
||||
rx_trainng_done[ap_nr][cp_nr][comphy_index] = 1;
|
||||
|
||||
return 0;
|
||||
|
|
@ -2273,12 +2227,16 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
|
|||
* the network registers like: MG, AP, MAC, PCS, Serdes etc.)
|
||||
*/
|
||||
static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base,
|
||||
uint8_t comphy_index)
|
||||
uint8_t comphy_index,
|
||||
uint32_t comphy_mode)
|
||||
{
|
||||
uint32_t mask, data;
|
||||
uintptr_t comphy_addr = comphy_addr =
|
||||
COMPHY_ADDR(comphy_base, comphy_index);
|
||||
|
||||
/* configure phy selector for XFI/SFI */
|
||||
mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index,
|
||||
comphy_mode);
|
||||
debug_enter();
|
||||
debug("stage: RFU configurations - hard reset comphy\n");
|
||||
/* RFU configurations - hard reset comphy */
|
||||
|
|
@ -2371,7 +2329,8 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
|
|||
comphy_mode);
|
||||
break;
|
||||
case (COMPHY_AP_MODE):
|
||||
err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index);
|
||||
err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index,
|
||||
comphy_mode);
|
||||
break;
|
||||
default:
|
||||
ERROR("comphy%d: unsupported comphy mode\n", comphy_index);
|
||||
|
|
|
|||
|
|
@ -13,19 +13,35 @@
|
|||
#define CACHE_LLC_H
|
||||
|
||||
#define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100)
|
||||
#define LLC_SECURE_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x10C)
|
||||
#define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700)
|
||||
#define L2X0_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C)
|
||||
#define L2X0_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC)
|
||||
#define L2X0_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC)
|
||||
#define LLC_TC0_LOCK(ap) (MVEBU_LLC_BASE(ap) + 0x920)
|
||||
#define LLC_BANKED_MNT_AHR(ap) (MVEBU_LLC_BASE(ap) + 0x724)
|
||||
#define LLC_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C)
|
||||
#define LLC_BLK_ALOC(ap) (MVEBU_LLC_BASE(ap) + 0x78c)
|
||||
#define LLC_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC)
|
||||
#define LLC_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC)
|
||||
#define LLC_TCN_LOCK(ap, tc) (MVEBU_LLC_BASE(ap) + 0x920 + 4 * (tc))
|
||||
|
||||
#define MASTER_LLC_CTRL LLC_CTRL(MVEBU_AP0)
|
||||
#define MASTER_L2X0_INV_WAY L2X0_INV_WAY(MVEBU_AP0)
|
||||
#define MASTER_LLC_TC0_LOCK LLC_TC0_LOCK(MVEBU_AP0)
|
||||
#define MASTER_LLC_INV_WAY LLC_INV_WAY(MVEBU_AP0)
|
||||
#define MASTER_LLC_TC0_LOCK LLC_TCN_LOCK(MVEBU_AP0, 0)
|
||||
|
||||
#define LLC_CTRL_EN 1
|
||||
#define LLC_EXCLUSIVE_EN 0x100
|
||||
#define LLC_WAY_MASK 0xFFFFFFFF
|
||||
#define LLC_ALL_WAYS_MASK 0xFFFFFFFF
|
||||
|
||||
/* AP806/AP807 - 1MB 8-ways LLC */
|
||||
#define LLC_WAYS 8
|
||||
#define LLC_WAY_MASK ((1 << LLC_WAYS) - 1)
|
||||
#define LLC_SIZE (1024 * 1024)
|
||||
#define LLC_WAY_SIZE (LLC_SIZE / LLC_WAYS)
|
||||
#define LLC_TC_NUM 15
|
||||
|
||||
#define LLC_BLK_ALOC_WAY_ID(way) ((way) & 0x1f)
|
||||
#define LLC_BLK_ALOC_WAY_DATA_DSBL (0x0 << 6)
|
||||
#define LLC_BLK_ALOC_WAY_DATA_CLR (0x1 << 6)
|
||||
#define LLC_BLK_ALOC_WAY_DATA_SET (0x3 << 6)
|
||||
#define LLC_BLK_ALOC_BASE_ADDR(addr) ((addr) & (LLC_WAY_SIZE - 1))
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
void llc_cache_sync(int ap_index);
|
||||
|
|
@ -36,6 +52,10 @@ void llc_disable(int ap_index);
|
|||
void llc_enable(int ap_index, int excl_mode);
|
||||
int llc_is_exclusive(int ap_index);
|
||||
void llc_runtime_enable(int ap_index);
|
||||
#endif
|
||||
#if LLC_SRAM
|
||||
void llc_sram_enable(int ap_index);
|
||||
void llc_sram_disable(int ap_index);
|
||||
#endif /* LLC_SRAM */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* CACHE_LLC_H */
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ void ccu_dram_win_config(int ap_index, struct addr_map_win *win);
|
|||
void ccu_dram_target_set(int ap_index, uint32_t target);
|
||||
void ccu_save_win_all(int ap_id);
|
||||
void ccu_restore_win_all(int ap_id);
|
||||
int ccu_is_win_enabled(int ap_index, uint32_t win_id);
|
||||
#endif
|
||||
|
||||
#endif /* CCU_H */
|
||||
|
|
|
|||
|
|
@ -71,6 +71,4 @@
|
|||
#define MAX_IO_DEVICES 3
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */
|
||||
|
||||
#endif /* BOARD_MARVELL_DEF_H */
|
||||
|
|
@ -49,15 +49,17 @@
|
|||
*/
|
||||
#define MARVELL_LOCAL_STATE_OFF 2
|
||||
|
||||
/* This leaves a gap between end of DRAM and start of ROM block */
|
||||
#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */
|
||||
|
||||
/* The first 4KB of Trusted SRAM are used as shared memory */
|
||||
#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
|
||||
#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
|
||||
#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE
|
||||
#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
|
||||
|
||||
/* The remaining Trusted SRAM is used to load the BL images */
|
||||
#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
|
||||
MARVELL_SHARED_RAM_SIZE)
|
||||
#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
|
||||
#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \
|
||||
MARVELL_SHARED_RAM_SIZE)
|
||||
|
||||
#define MARVELL_DRAM_BASE ULL(0x0)
|
||||
|
|
@ -65,7 +67,7 @@
|
|||
#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \
|
||||
MARVELL_DRAM_SIZE - 1)
|
||||
|
||||
#define MARVELL_IRQ_SEC_PHY_TIMER 29
|
||||
#define MARVELL_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
#define MARVELL_IRQ_SEC_SGI_0 8
|
||||
#define MARVELL_IRQ_SEC_SGI_1 9
|
||||
|
|
@ -86,7 +88,6 @@
|
|||
MARVELL_DRAM_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_NS)
|
||||
|
||||
|
||||
/*
|
||||
* The number of regions like RO(code), coherent and data required by
|
||||
* different BL stages which need to be mapped in the MMU.
|
||||
|
|
@ -173,5 +174,15 @@
|
|||
#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
|
||||
MARVELL_BL_RAM_SIZE)
|
||||
|
||||
/*****************************************************************************
|
||||
* BL32 specific defines.
|
||||
*****************************************************************************
|
||||
*/
|
||||
#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
|
||||
#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE)
|
||||
|
||||
#ifdef SPD_none
|
||||
#undef BL32_BASE
|
||||
#endif /* SPD_none */
|
||||
|
||||
#endif /* MARVELL_DEF_H */
|
||||
|
|
@ -71,7 +71,4 @@
|
|||
#define MAX_IO_DEVICES 3
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */
|
||||
|
||||
|
||||
#endif /* BOARD_MARVELL_DEF_H */
|
||||
|
|
|
|||
|
|
@ -47,15 +47,17 @@
|
|||
*/
|
||||
#define MARVELL_LOCAL_STATE_OFF 2
|
||||
|
||||
/* This leaves a gap between end of DRAM and start of ROM block */
|
||||
#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */
|
||||
|
||||
/* The first 4KB of Trusted SRAM are used as shared memory */
|
||||
#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
|
||||
#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
|
||||
#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE
|
||||
#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
|
||||
|
||||
/* The remaining Trusted SRAM is used to load the BL images */
|
||||
#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
|
||||
MARVELL_SHARED_RAM_SIZE)
|
||||
#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
|
||||
#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \
|
||||
MARVELL_SHARED_RAM_SIZE)
|
||||
/* Non-shared DRAM */
|
||||
#define MARVELL_DRAM_BASE ULL(0x0)
|
||||
|
|
@ -75,9 +77,40 @@
|
|||
#define MARVELL_IRQ_SEC_SGI_6 14
|
||||
#define MARVELL_IRQ_SEC_SGI_7 15
|
||||
|
||||
#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \
|
||||
MARVELL_SHARED_RAM_BASE,\
|
||||
MARVELL_SHARED_RAM_SIZE,\
|
||||
#ifdef SPD_opteed
|
||||
/*
|
||||
* BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
|
||||
* load/authenticate the trusted os extra image. The first 512KB of
|
||||
* TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
|
||||
* for OPTEE is paged image which only include the paging part using
|
||||
* virtual memory but without "init" data. OPTEE will copy the "init" data
|
||||
* (from pager image) to the first 512KB of TZC_DRAM, and then copy the
|
||||
* extra image behind the "init" data.
|
||||
*/
|
||||
#define MARVELL_OPTEE_PAGEABLE_LOAD_BASE \
|
||||
(PLAT_MARVELL_TRUSTED_RAM_BASE + \
|
||||
PLAT_MARVELL_TRUSTED_RAM_SIZE - \
|
||||
MARVELL_OPTEE_PAGEABLE_LOAD_SIZE)
|
||||
#define MARVELL_OPTEE_PAGEABLE_LOAD_SIZE 0x400000
|
||||
#define MARVELL_OPTEE_PAGEABLE_LOAD_MEM \
|
||||
MAP_REGION_FLAT( \
|
||||
MARVELL_OPTEE_PAGEABLE_LOAD_BASE, \
|
||||
MARVELL_OPTEE_PAGEABLE_LOAD_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
|
||||
/*
|
||||
* Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
|
||||
* support is enabled).
|
||||
*/
|
||||
#define MARVELL_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
|
||||
BL32_BASE, \
|
||||
BL32_LIMIT - BL32_BASE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
#endif /* SPD_opteed */
|
||||
|
||||
#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \
|
||||
MARVELL_SHARED_RAM_BASE, \
|
||||
MARVELL_SHARED_RAM_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
|
||||
#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
|
||||
|
|
@ -85,7 +118,6 @@
|
|||
MARVELL_DRAM_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_NS)
|
||||
|
||||
|
||||
/*
|
||||
* The number of regions like RO(code), coherent and data required by
|
||||
* different BL stages which need to be mapped in the MMU.
|
||||
|
|
@ -177,5 +209,14 @@
|
|||
#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
|
||||
MARVELL_BL_RAM_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL32 specific defines.
|
||||
******************************************************************************/
|
||||
#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
|
||||
#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE)
|
||||
|
||||
#ifdef SPD_none
|
||||
#undef BL32_BASE
|
||||
#endif /* SPD_none */
|
||||
|
||||
#endif /* MARVELL_DEF_H */
|
||||
|
|
|
|||
|
|
@ -5,6 +5,6 @@
|
|||
# https://spdx.org/licenses
|
||||
#
|
||||
|
||||
include plat/marvell/armada/a3700/common/a3700_common.mk
|
||||
include plat/marvell/armada/a3k/common/a3700_common.mk
|
||||
|
||||
include plat/marvell/armada/common/marvell_common.mk
|
||||
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
MARVELL_PLAT_BASE := plat/marvell/armada
|
||||
MARVELL_PLAT_INCLUDE_BASE := include/plat/marvell/armada
|
||||
PLAT_FAMILY := a3700
|
||||
PLAT_FAMILY := a3k
|
||||
PLAT_FAMILY_BASE := $(MARVELL_PLAT_BASE)/$(PLAT_FAMILY)
|
||||
PLAT_INCLUDE_BASE := $(MARVELL_PLAT_INCLUDE_BASE)/$(PLAT_FAMILY)
|
||||
PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common
|
||||
|
|
@ -81,11 +81,11 @@
|
|||
#define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2)
|
||||
/* DRAM[2MB..66MB] is used as Trusted ROM */
|
||||
#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
|
||||
/* 64 MB TODO: reduce this to minimum needed according to fip image size*/
|
||||
#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
|
||||
/* 4 MB for FIP image */
|
||||
#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000
|
||||
/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
|
||||
#define PLAT_MARVELL_TRUSTED_DRAM_BASE 0x04400000
|
||||
#define PLAT_MARVELL_TRUSTED_DRAM_SIZE 0x01000000 /* 16 MB */
|
||||
#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
|
||||
#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x01000000 /* 16 MB */
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
|
||||
|
|
@ -169,8 +169,7 @@
|
|||
#define PLAT_MARVELL_NSTIMER_FRAME_ID 1
|
||||
|
||||
/* Mailbox base address */
|
||||
#define PLAT_MARVELL_MAILBOX_BASE \
|
||||
(MARVELL_TRUSTED_SRAM_BASE + 0x400)
|
||||
#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE + 0x400)
|
||||
#define PLAT_MARVELL_MAILBOX_SIZE 0x100
|
||||
#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
|
||||
|
||||
|
|
@ -221,12 +220,4 @@
|
|||
/* Securities */
|
||||
#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
|
||||
|
||||
#define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
|
||||
#define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE
|
||||
|
||||
#ifdef BL32
|
||||
#define BL32_BASE TRUSTED_DRAM_BASE
|
||||
#define BL32_LIMIT TRUSTED_DRAM_SIZE
|
||||
#endif
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -102,6 +102,9 @@ struct addr_map_win ccu_memory_map[] = { /* IO window */
|
|||
#ifdef IMAGE_BLE
|
||||
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
|
||||
#else
|
||||
#if LLC_SRAM
|
||||
{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
|
||||
#endif
|
||||
{0x00000000f2000000, 0xe000000, IO_0_TID},
|
||||
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
|
||||
{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
|
||||
|
|
|
|||
|
|
@ -93,6 +93,9 @@ struct addr_map_win ccu_memory_map[] = {
|
|||
#ifdef IMAGE_BLE
|
||||
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
|
||||
#else
|
||||
#if LLC_SRAM
|
||||
{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
|
||||
#endif
|
||||
{0x00000000f2000000, 0xe000000, IO_0_TID},
|
||||
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
|
||||
{0x0000000800000000, 0x200000000, IO_0_TID}, /* IO window */
|
||||
|
|
|
|||
|
|
@ -131,6 +131,9 @@ struct addr_map_win ccu_memory_map[] = {
|
|||
#ifdef IMAGE_BLE
|
||||
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
|
||||
#else
|
||||
#if LLC_SRAM
|
||||
{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
|
||||
#endif
|
||||
{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
|
||||
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
|
||||
{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
|
||||
|
|
|
|||
|
|
@ -165,6 +165,9 @@ struct addr_map_win ccu_memory_map[] = {
|
|||
#ifdef IMAGE_BLE
|
||||
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
|
||||
#else
|
||||
#if LLC_SRAM
|
||||
{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
|
||||
#endif
|
||||
{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
|
||||
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
|
||||
{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
|||
plat/common/plat_gicv2.c
|
||||
|
||||
PLAT_INCLUDES := -I$(BOARD_DIR) \
|
||||
-I$(BOARD_DIR)/board \
|
||||
-I$(PLAT_COMMON_BASE)/include \
|
||||
-I$(PLAT_INCLUDE_BASE)/common
|
||||
|
||||
|
|
|
|||
|
|
@ -18,22 +18,27 @@
|
|||
*/
|
||||
#if IMAGE_BL1
|
||||
const mmap_region_t plat_marvell_mmap[] = {
|
||||
MARVELL_MAP_SHARED_RAM,
|
||||
MARVELL_MAP_SECURE_RAM,
|
||||
MAP_DEVICE0,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
#if IMAGE_BL2
|
||||
const mmap_region_t plat_marvell_mmap[] = {
|
||||
MARVELL_MAP_SHARED_RAM,
|
||||
MARVELL_MAP_SECURE_RAM,
|
||||
MAP_DEVICE0,
|
||||
MARVELL_MAP_DRAM,
|
||||
#ifdef SPD_opteed
|
||||
MARVELL_MAP_OPTEE_CORE_MEM,
|
||||
MARVELL_OPTEE_PAGEABLE_LOAD_MEM,
|
||||
#endif
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IMAGE_BL2U
|
||||
const mmap_region_t plat_marvell_mmap[] = {
|
||||
MARVELL_MAP_SECURE_RAM,
|
||||
MAP_DEVICE0,
|
||||
{0}
|
||||
};
|
||||
|
|
@ -48,7 +53,7 @@ const mmap_region_t plat_marvell_mmap[] = {
|
|||
|
||||
#if IMAGE_BL31
|
||||
const mmap_region_t plat_marvell_mmap[] = {
|
||||
MARVELL_MAP_SHARED_RAM,
|
||||
MARVELL_MAP_SECURE_RAM,
|
||||
MAP_DEVICE0,
|
||||
MARVELL_MAP_DRAM,
|
||||
{0}
|
||||
|
|
@ -56,6 +61,7 @@ const mmap_region_t plat_marvell_mmap[] = {
|
|||
#endif
|
||||
#if IMAGE_BL32
|
||||
const mmap_region_t plat_marvell_mmap[] = {
|
||||
MARVELL_MAP_SECURE_RAM,
|
||||
MAP_DEVICE0,
|
||||
{0}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -92,13 +92,16 @@
|
|||
#define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \
|
||||
PLAT_MARVELL_CLUSTER_CORE_COUNT)
|
||||
|
||||
/* DRAM[2MB..66MB] is used as Trusted ROM */
|
||||
/* Part of DRAM that is used as Trusted ROM */
|
||||
#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
|
||||
/* 64 MB TODO: reduce this to minimum needed according to fip image size */
|
||||
#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
|
||||
/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
|
||||
#define PLAT_MARVELL_TRUSTED_DRAM_BASE 0x04400000
|
||||
#define PLAT_MARVELL_TRUSTED_DRAM_SIZE 0x01000000 /* 16 MB */
|
||||
/* 4 MB for FIP image */
|
||||
#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000
|
||||
/* Reserve 16M for SCP (Secure PayLoad) Trusted RAM */
|
||||
#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
|
||||
#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x01000000 /* 16 MB DRAM */
|
||||
|
||||
#define PLAT_MARVELL_LLC_SRAM_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
|
||||
#define PLAT_MARVELL_LLC_SRAM_SIZE 0x00100000 /* 1 MB SRAM */
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
|
||||
|
|
@ -182,22 +185,14 @@
|
|||
/* Mailbox base address (note the lower memory space
|
||||
* is reserved for BLE data)
|
||||
*/
|
||||
#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE \
|
||||
+ 0x400)
|
||||
#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE \
|
||||
+ 0x400)
|
||||
#define PLAT_MARVELL_MAILBOX_SIZE 0x100
|
||||
#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
|
||||
|
||||
/* Securities */
|
||||
#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
|
||||
|
||||
#define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
|
||||
#define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE
|
||||
|
||||
#ifdef BL32
|
||||
#define BL32_BASE TRUSTED_DRAM_BASE
|
||||
#define BL32_LIMIT TRUSTED_DRAM_SIZE
|
||||
#endif
|
||||
|
||||
#define MVEBU_PMU_IRQ_WA
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/marvell/ccu.h>
|
||||
#include <drivers/marvell/mochi/ap_setup.h>
|
||||
#include <drivers/marvell/mochi/cp110_setup.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
|
|
@ -18,9 +19,6 @@
|
|||
|
||||
#include "mss_scp_bootloader.h"
|
||||
|
||||
/* IO windows configuration */
|
||||
#define IOW_GCR_OFFSET (0x70)
|
||||
|
||||
/* MSS windows configuration */
|
||||
#define MSS_AEBR(base) (base + 0x160)
|
||||
#define MSS_AIBR(base) (base + 0x164)
|
||||
|
|
@ -51,7 +49,7 @@ struct addr_map_win ccu_mem_map[] = {
|
|||
*/
|
||||
static int bl2_plat_mmap_init(void)
|
||||
{
|
||||
int cfg_num, win_id, cfg_idx;
|
||||
int cfg_num, win_id, cfg_idx, cp;
|
||||
|
||||
cfg_num = ARRAY_SIZE(ccu_mem_map);
|
||||
|
||||
|
|
@ -65,20 +63,29 @@ static int bl2_plat_mmap_init(void)
|
|||
* Do not touch CCU window 0,
|
||||
* it's used for the internal registers access
|
||||
*/
|
||||
for (cfg_idx = 0, win_id = 1; cfg_idx < cfg_num; cfg_idx++, win_id++) {
|
||||
for (cfg_idx = 0, win_id = 1;
|
||||
(win_id < MVEBU_CCU_MAX_WINS) && (cfg_idx < cfg_num); win_id++) {
|
||||
/* Skip already enabled CCU windows */
|
||||
if (ccu_is_win_enabled(MVEBU_AP0, win_id))
|
||||
continue;
|
||||
/* Enable required CCU windows */
|
||||
ccu_win_check(&ccu_mem_map[cfg_idx]);
|
||||
ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
|
||||
cfg_idx++;
|
||||
}
|
||||
|
||||
/* Set the default target id to PIDI */
|
||||
mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
|
||||
/* Config address for each cp other than cp0 */
|
||||
for (cp = 1; cp < CP_COUNT; cp++)
|
||||
update_cp110_default_win(cp);
|
||||
|
||||
/* There is need to configure IO_WIN windows again to overwrite
|
||||
* temporary configuration done during update_cp110_default_win
|
||||
*/
|
||||
init_io_win(MVEBU_AP0);
|
||||
|
||||
/* Open AMB bridge required for MG access */
|
||||
cp110_amb_init(MVEBU_CP_REGS_BASE(0));
|
||||
|
||||
if (CP_COUNT == 2)
|
||||
cp110_amb_init(MVEBU_CP_REGS_BASE(1));
|
||||
for (cp = 0; cp < CP_COUNT; cp++)
|
||||
cp110_amb_init(MVEBU_CP_REGS_BASE(cp));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -116,21 +116,12 @@ void bl31_plat_arch_setup(void)
|
|||
marvell_bl31_plat_arch_setup();
|
||||
|
||||
for (cp = 0; cp < CP_COUNT; cp++) {
|
||||
if (cp >= 1)
|
||||
update_cp110_default_win(cp);
|
||||
|
||||
cp110_init(MVEBU_CP_REGS_BASE(cp),
|
||||
STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
|
||||
|
||||
marvell_bl31_mpp_init(cp);
|
||||
}
|
||||
|
||||
/*
|
||||
* There is need to configure IO_WIN windows again to overwrite
|
||||
* temporary configuration done during update_cp110_default_win
|
||||
*/
|
||||
init_io_win(MVEBU_AP0);
|
||||
|
||||
for (cp = 1; cp < CP_COUNT; cp++)
|
||||
mci_link_tune(cp - 1);
|
||||
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@ func disable_sram
|
|||
|
||||
/* Invalidate all ways */
|
||||
ldr w1, =LLC_WAY_MASK
|
||||
ldr x0, =MASTER_L2X0_INV_WAY
|
||||
ldr x0, =MASTER_LLC_INV_WAY
|
||||
str w1, [x0]
|
||||
|
||||
/* Finally disable LLC */
|
||||
|
|
|
|||
|
|
@ -16,8 +16,21 @@ SEPARATE_CODE_AND_RODATA := 1
|
|||
# flag to switch from PLL to ARO
|
||||
ARO_ENABLE := 0
|
||||
$(eval $(call add_define,ARO_ENABLE))
|
||||
|
||||
# Convert LLC to secure SRAM
|
||||
LLC_SRAM := 0
|
||||
$(eval $(call add_define,LLC_SRAM))
|
||||
|
||||
# Enable/Disable LLC
|
||||
ifeq (${LLC_SRAM}, 0)
|
||||
LLC_ENABLE := 1
|
||||
else
|
||||
# When LLC_SRAM=1, the entire LLC converted to SRAM and enabled at BL1.
|
||||
# All existing cases activating LLC at BL31 stage should be disabled.
|
||||
# The below assignment does not allow changing the LLC_ENABLE
|
||||
# value in the command line.
|
||||
LLC_ENABLE = 0
|
||||
endif
|
||||
$(eval $(call add_define,LLC_ENABLE))
|
||||
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue