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https://github.com/ARM-software/arm-trusted-firmware.git
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b5c850d48d
The Marvell Armada 37xx SoCs-based platforms contain a bit awkward directory structure because the currently only one supported PLAT and PLAT_FAMILY are the same. Modify the latter to 'a3k' in order to improve it and keep plat/marvell/armada tree more consistent: plat/marvell/ ├── armada │ ├── a3k │ │ ├── a3700 [...] │ ├── a8k │ │ ├── a70x0 [...] Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a Signed-off-by: Marcin Wojtas <mw@semihalf.com>
70 lines
2 KiB
C
70 lines
2 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <lib/mmio.h>
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#include <armada_common.h>
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#include <dram_win.h>
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#include <io_addr_dec.h>
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#include <marvell_plat_priv.h>
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#include <plat_marvell.h>
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/* This routine does MPP initialization */
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static void marvell_bl31_mpp_init(void)
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{
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mmio_clrbits_32(MVEBU_NB_GPIO_SEL_REG, 1 << MVEBU_GPIO_TW1_GPIO_EN_OFF);
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/* Set hidden GPIO setting for SPI.
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* In north_bridge_pin_out_en_high register 13804,
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* bit 28 is the one which enables CS, CLK pins to be
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* output, need to set it to 1.
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* The initial value of this bit is 1, but in UART boot mode
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* initialization, this bit is disabled and the SPI CS and CLK pins
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* are used for downloading image purpose; so after downloading,
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* we should set this bit to 1 again to enable SPI CS and CLK pins.
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* And anyway, this bit value should be 1 in all modes,
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* so here we does not judge boot mode and set this bit to 1 always.
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*/
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mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG,
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1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF);
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}
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/* This function overruns the same function in marvell_bl31_setup.c */
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void bl31_plat_arch_setup(void)
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{
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struct dec_win_config *io_dec_map;
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uint32_t dec_win_num;
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struct dram_win_map dram_wins_map;
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marvell_bl31_plat_arch_setup();
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/* MPP init */
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marvell_bl31_mpp_init();
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/* initialize the timer for delay functionality */
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plat_delay_timer_init();
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/* CPU address decoder windows initialization. */
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cpu_wins_init();
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/* fetch CPU-DRAM window mapping information by reading
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* CPU-DRAM decode windows (only the enabled ones)
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*/
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dram_win_map_build(&dram_wins_map);
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/* Get IO address decoder windows */
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if (marvell_get_io_dec_win_conf(&io_dec_map, &dec_win_num)) {
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printf("No IO address decoder windows configurations found!\n");
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return;
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}
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/* IO address decoder init */
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if (init_io_addr_dec(&dram_wins_map, io_dec_map, dec_win_num)) {
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printf("IO address decoder windows initialization failed!\n");
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return;
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}
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}
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