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The Marvell Armada 37xx SoCs-based platforms contain a bit awkward directory structure because the currently only one supported PLAT and PLAT_FAMILY are the same. Modify the latter to 'a3k' in order to improve it and keep plat/marvell/armada tree more consistent: plat/marvell/ ├── armada │ ├── a3k │ │ ├── a3700 [...] │ ├── a8k │ │ ├── a70x0 [...] Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a Signed-off-by: Marcin Wojtas <mw@semihalf.com>
53 lines
968 B
C
53 lines
968 B
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <plat_marvell.h>
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/* MMU entry for internal (register) space access */
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#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
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DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* Table of regions for various BL stages to map using the MMU.
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*/
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#if IMAGE_BL1
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const mmap_region_t plat_marvell_mmap[] = {
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MARVELL_MAP_SHARED_RAM,
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MAP_DEVICE0,
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{0}
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};
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#endif
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#if IMAGE_BL2
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const mmap_region_t plat_marvell_mmap[] = {
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MARVELL_MAP_SHARED_RAM,
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MAP_DEVICE0,
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MARVELL_MAP_DRAM,
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{0}
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};
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#endif
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#if IMAGE_BL2U
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const mmap_region_t plat_marvell_mmap[] = {
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MAP_DEVICE0,
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{0}
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};
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#endif
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#if IMAGE_BL31
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const mmap_region_t plat_marvell_mmap[] = {
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MARVELL_MAP_SHARED_RAM,
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MAP_DEVICE0,
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MARVELL_MAP_DRAM,
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{0}
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};
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#endif
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#if IMAGE_BL32
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const mmap_region_t plat_marvell_mmap[] = {
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MAP_DEVICE0,
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{0}
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};
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#endif
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MARVELL_CASSERT_MMAP;
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