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The Marvell Armada 37xx SoCs-based platforms contain a bit awkward directory structure because the currently only one supported PLAT and PLAT_FAMILY are the same. Modify the latter to 'a3k' in order to improve it and keep plat/marvell/armada tree more consistent: plat/marvell/ ├── armada │ ├── a3k │ │ ├── a3700 [...] │ ├── a8k │ │ ├── a70x0 [...] Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a Signed-off-by: Marcin Wojtas <mw@semihalf.com>
34 lines
1.1 KiB
C
34 lines
1.1 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <common/bl_common.h>
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#include <io_addr_dec.h>
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#include <mvebu_def.h>
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struct dec_win_config io_dec_win_conf[] = {
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/* dec_reg_base win_attr max_dram_win max_remap win_offset */
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{0xc000, 0x3d, 2, 0, 0x08}, /* USB */
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{0xc100, 0x3d, 3, 0, 0x10}, /* USB3 */
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{0xc200, 0x3d, 2, 0, 0x10}, /* DMA */
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{0xc300, 0x3d, 2, 0, 0x10}, /* NETA0 */
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{0xc400, 0x3d, 2, 0, 0x10}, /* NETA1 */
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{0xc500, 0x3d, 2, 0, 0x10}, /* PCIe */
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{0xc800, 0x3d, 3, 0, 0x10}, /* SATA */
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{0xca00, 0x3d, 3, 0, 0x08}, /* SD */
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{0xcb00, 0x3d, 3, 0, 0x10}, /* eMMC */
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{0xce00, 0x3d, 2, 0, 0x08}, /* EIP97 */
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};
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int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size)
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{
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*win = io_dec_win_conf;
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*size = sizeof(io_dec_win_conf)/sizeof(struct dec_win_config);
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return 0;
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}
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