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https://github.com/ARM-software/arm-trusted-firmware.git
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b5c850d48d
The Marvell Armada 37xx SoCs-based platforms contain a bit awkward directory structure because the currently only one supported PLAT and PLAT_FAMILY are the same. Modify the latter to 'a3k' in order to improve it and keep plat/marvell/armada tree more consistent: plat/marvell/ ├── armada │ ├── a3k │ │ ├── a3700 [...] │ ├── a8k │ │ ├── a70x0 [...] Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a Signed-off-by: Marcin Wojtas <mw@semihalf.com>
122 lines
4.5 KiB
C
122 lines
4.5 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef A3700_PLAT_DEF_H
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#define A3700_PLAT_DEF_H
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#include <marvell_def.h>
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#define MVEBU_MAX_CPUS_PER_CLUSTER 2
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#define MVEBU_PRIMARY_CPU 0x0
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/*
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* The counter on A3700 is always fed from reference 25M clock (XTAL).
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* However minimal CPU counter prescaler is 2, so the counter
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* frequency will be divided by 2, the number is 12.5M
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*/
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#define COUNTER_FREQUENCY 12500000
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#define MVEBU_REGS_BASE 0xD0000000
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/*****************************************************************************
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* MVEBU memory map related constants
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*****************************************************************************
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*/
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE MVEBU_REGS_BASE
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#define DEVICE0_SIZE 0x10000000
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/*****************************************************************************
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* GIC-500 & interrupt handling related constants
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*****************************************************************************
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*/
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/* Base MVEBU compatible GIC memory map */
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#define MVEBU_GICD_BASE 0x1D00000
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#define MVEBU_GICR_BASE 0x1D40000
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#define MVEBU_GICC_BASE 0x1D80000
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/* CCI-400 */
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#define MVEBU_CCI_BASE 0x8000000
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/*****************************************************************************
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* North and south bridge register base
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*****************************************************************************
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*/
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#define MVEBU_NB_REGS_BASE (MVEBU_REGS_BASE + 0x13000)
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#define MVEBU_SB_REGS_BASE (MVEBU_REGS_BASE + 0x18000)
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/*****************************************************************************
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* GPIO registers related constants
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*****************************************************************************
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*/
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/* North and south bridge GPIO register base address */
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#define MVEBU_NB_GPIO_REG_BASE (MVEBU_NB_REGS_BASE + 0x800)
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#define MVEBU_NB_GPIO_IRQ_REG_BASE (MVEBU_NB_REGS_BASE + 0xC00)
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#define MVEBU_SB_GPIO_REG_BASE (MVEBU_SB_REGS_BASE + 0x800)
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#define MVEBU_SB_GPIO_IRQ_REG_BASE (MVEBU_SB_REGS_BASE + 0xC00)
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#define MVEBU_NB_SB_IRQ_REG_BASE (MVEBU_REGS_BASE + 0x8A00)
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/* North Bridge GPIO selection register */
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#define MVEBU_NB_GPIO_SEL_REG (MVEBU_NB_GPIO_REG_BASE + 0x30)
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#define MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG (MVEBU_NB_GPIO_REG_BASE + 0x04)
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/* I2C1 GPIO Enable bit offset */
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#define MVEBU_GPIO_TW1_GPIO_EN_OFF (10)
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/* SPI pins mode bit offset */
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#define MVEBU_GPIO_NB_SPI_PIN_MODE_OFF (28)
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/*****************************************************************************
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* DRAM registers related constants
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*****************************************************************************
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*/
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#define MVEBU_DRAM_REG_BASE (MVEBU_REGS_BASE)
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/*****************************************************************************
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* SB wake-up registers related constants
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*****************************************************************************
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*/
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#define MVEBU_SB_WAKEUP_REG_BASE (MVEBU_REGS_BASE + 0x19000)
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/*****************************************************************************
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* PMSU registers related constants
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*****************************************************************************
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*/
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#define MVEBU_PMSU_REG_BASE (MVEBU_REGS_BASE + 0x14000)
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/*****************************************************************************
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* North Bridge Step-Down Registers
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*****************************************************************************
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*/
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#define MVEBU_NB_STEP_DOWN_REG_BASE (MVEBU_REGS_BASE + 0x12800)
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/*****************************************************************************
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* DRAM CS memory map register base
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*****************************************************************************
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*/
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#define MVEBU_CS_MMAP_REG_BASE (MVEBU_REGS_BASE + 0x200)
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/*****************************************************************************
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* CPU decoder window registers related constants
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*****************************************************************************
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*/
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#define MVEBU_CPU_DEC_WIN_REG_BASE (MVEBU_REGS_BASE + 0xCF00)
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/*****************************************************************************
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* AVS registers related constants
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*****************************************************************************
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*/
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#define MVEBU_AVS_REG_BASE (MVEBU_REGS_BASE + 0x11500)
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/*****************************************************************************
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* AVS registers related constants
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*****************************************************************************
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*/
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#define MVEBU_COMPHY_REG_BASE (MVEBU_REGS_BASE + 0x18300)
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#endif /* A3700_PLAT_DEF_H */
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