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c96aa7fb3d
Make sure the current CCU window is not in use before adding a new address map during MSS BL2 image load preparations. At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is added to MSS BL2 stage initialization, the DDR entry will be destroyed and lead to the system hang. Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
158 lines
4.3 KiB
C
158 lines
4.3 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/marvell/ccu.h>
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#include <drivers/marvell/mochi/ap_setup.h>
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#include <drivers/marvell/mochi/cp110_setup.h>
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#include <lib/mmio.h>
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#include <armada_common.h>
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#include <marvell_plat_priv.h> /* timer functionality */
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#include "mss_scp_bootloader.h"
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/* MSS windows configuration */
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#define MSS_AEBR(base) (base + 0x160)
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#define MSS_AIBR(base) (base + 0x164)
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#define MSS_AEBR_MASK 0xFFF
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#define MSS_AIBR_MASK 0xFFF
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#define MSS_EXTERNAL_SPACE 0x50000000
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#define MSS_EXTERNAL_ACCESS_BIT 28
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#define MSS_EXTERNAL_ADDR_MASK 0xfffffff
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#define MSS_INTERNAL_ACCESS_BIT 28
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struct addr_map_win ccu_mem_map[] = {
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{MVEBU_CP_REGS_BASE(0), 0x4000000, IO_0_TID}
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};
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/* Since the scp_bl2 image can contain firmware for cp1 and cp0 coprocessors,
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* the access to cp0 and cp1 need to be provided. More precisely it is
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* required to:
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* - get the information about device id which is stored in CP0 registers
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* (to distinguish between cases where we have cp0 and cp1 or standalone cp0)
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* - get the access to cp which is needed for loading fw for cp0/cp1
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* coprocessors
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* This function configures ccu windows accordingly.
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*
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* Note: there is no need to restore previous ccu configuration, since in next
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* phase (BL31) the init_ccu will be called (via apn806_init/
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* bl31_plat_arch_setu) and therefore the ccu configuration will be overwritten.
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*/
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static int bl2_plat_mmap_init(void)
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{
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int cfg_num, win_id, cfg_idx, cp;
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cfg_num = ARRAY_SIZE(ccu_mem_map);
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/* CCU window-0 should not be counted - it's already used */
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if (cfg_num > (MVEBU_CCU_MAX_WINS - 1)) {
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ERROR("BL2: %s: trying to open too many windows\n", __func__);
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return -1;
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}
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/* Enable required CCU windows
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* Do not touch CCU window 0,
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* it's used for the internal registers access
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*/
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for (cfg_idx = 0, win_id = 1;
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(win_id < MVEBU_CCU_MAX_WINS) && (cfg_idx < cfg_num); win_id++) {
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/* Skip already enabled CCU windows */
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if (ccu_is_win_enabled(MVEBU_AP0, win_id))
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continue;
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/* Enable required CCU windows */
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ccu_win_check(&ccu_mem_map[cfg_idx]);
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ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
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cfg_idx++;
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}
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/* Config address for each cp other than cp0 */
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for (cp = 1; cp < CP_COUNT; cp++)
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update_cp110_default_win(cp);
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/* There is need to configure IO_WIN windows again to overwrite
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* temporary configuration done during update_cp110_default_win
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*/
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init_io_win(MVEBU_AP0);
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/* Open AMB bridge required for MG access */
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for (cp = 0; cp < CP_COUNT; cp++)
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cp110_amb_init(MVEBU_CP_REGS_BASE(cp));
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return 0;
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}
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/*****************************************************************************
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* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
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* Return 0 on success, -1 otherwise.
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*****************************************************************************
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*/
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int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
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{
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int ret;
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INFO("BL2: Initiating SCP_BL2 transfer to SCP\n");
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/* initialize time (for delay functionality) */
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plat_delay_timer_init();
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ret = bl2_plat_mmap_init();
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if (ret != 0)
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return ret;
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ret = scp_bootloader_transfer((void *)scp_bl2_image_info->image_base,
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scp_bl2_image_info->image_size);
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if (ret == 0)
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INFO("BL2: SCP_BL2 transferred to SCP\n");
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else
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ERROR("BL2: SCP_BL2 transfer failure\n");
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return ret;
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}
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uintptr_t bl2_plat_get_cp_mss_regs(int ap_idx, int cp_idx)
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{
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return MVEBU_CP_REGS_BASE(cp_idx) + 0x280000;
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}
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uintptr_t bl2_plat_get_ap_mss_regs(int ap_idx)
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{
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return MVEBU_REGS_BASE + 0x580000;
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}
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uint32_t bl2_plat_get_cp_count(int ap_idx)
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{
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uint32_t revision = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
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/* A8040: two CPs.
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* A7040: one CP.
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*/
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if (revision == MVEBU_80X0_DEV_ID ||
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revision == MVEBU_80X0_CP115_DEV_ID)
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return 2;
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else
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return 1;
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}
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uint32_t bl2_plat_get_ap_count(void)
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{
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/* A8040 and A7040 have only one AP */
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return 1;
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}
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void bl2_plat_configure_mss_windows(uintptr_t mss_regs)
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{
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/* set AXI External and Internal Address Bus extension */
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mmio_write_32(MSS_AEBR(mss_regs),
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((0x0 >> MSS_EXTERNAL_ACCESS_BIT) & MSS_AEBR_MASK));
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mmio_write_32(MSS_AIBR(mss_regs),
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((mss_regs >> MSS_INTERNAL_ACCESS_BIT) & MSS_AIBR_MASK));
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}
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