From b5c850d48d49fd1afc3b8189bc2390f53770d4de Mon Sep 17 00:00:00 2001
From: Marcin Wojtas <mw@semihalf.com>
Date: Thu, 18 Jun 2020 19:50:47 +0200
Subject: [PATCH 01/15] plat: marvell: armada: modify PLAT_FAMILY name for 37xx
SoCs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The Marvell Armada 37xx SoCs-based platforms contain a bit
awkward directory structure because the currently only one
supported PLAT and PLAT_FAMILY are the same. Modify the latter
to 'a3k' in order to improve it and keep plat/marvell/armada
tree more consistent:
plat/marvell/
├── armada
│ ├── a3k
│ │ ├── a3700
[...]
│ ├── a8k
│ │ ├── a70x0
[...]
Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
.../plat/marvell/armada/{a3700 => a3k}/common/armada_common.h | 0
.../marvell/armada/{a3700 => a3k}/common/board_marvell_def.h | 0
include/plat/marvell/armada/{a3700 => a3k}/common/marvell_def.h | 0
.../plat/marvell/armada/{a3700 => a3k}/common/plat_marvell.h | 0
plat/marvell/armada/{a3700 => a3k}/a3700/board/pm_src.c | 0
plat/marvell/armada/{a3700 => a3k}/a3700/mvebu_def.h | 0
plat/marvell/armada/{a3700 => a3k}/a3700/plat_bl31_setup.c | 0
plat/marvell/armada/{a3700 => a3k}/a3700/platform.mk | 2 +-
plat/marvell/armada/{a3700 => a3k}/common/a3700_common.mk | 2 +-
plat/marvell/armada/{a3700 => a3k}/common/a3700_ea.c | 0
plat/marvell/armada/{a3700 => a3k}/common/a3700_sip_svc.c | 0
.../marvell/armada/{a3700 => a3k}/common/aarch64/a3700_common.c | 0
.../marvell/armada/{a3700 => a3k}/common/aarch64/plat_helpers.S | 0
plat/marvell/armada/{a3700 => a3k}/common/dram_win.c | 0
.../armada/{a3700 => a3k}/common/include/a3700_plat_def.h | 0
plat/marvell/armada/{a3700 => a3k}/common/include/a3700_pm.h | 0
plat/marvell/armada/{a3700 => a3k}/common/include/ddr_info.h | 0
plat/marvell/armada/{a3700 => a3k}/common/include/dram_win.h | 0
plat/marvell/armada/{a3700 => a3k}/common/include/io_addr_dec.h | 0
plat/marvell/armada/{a3700 => a3k}/common/include/plat_macros.S | 0
.../marvell/armada/{a3700 => a3k}/common/include/platform_def.h | 0
plat/marvell/armada/{a3700 => a3k}/common/io_addr_dec.c | 0
plat/marvell/armada/{a3700 => a3k}/common/marvell_plat_config.c | 0
plat/marvell/armada/{a3700 => a3k}/common/plat_pm.c | 0
24 files changed, 2 insertions(+), 2 deletions(-)
rename include/plat/marvell/armada/{a3700 => a3k}/common/armada_common.h (100%)
rename include/plat/marvell/armada/{a3700 => a3k}/common/board_marvell_def.h (100%)
rename include/plat/marvell/armada/{a3700 => a3k}/common/marvell_def.h (100%)
rename include/plat/marvell/armada/{a3700 => a3k}/common/plat_marvell.h (100%)
rename plat/marvell/armada/{a3700 => a3k}/a3700/board/pm_src.c (100%)
rename plat/marvell/armada/{a3700 => a3k}/a3700/mvebu_def.h (100%)
rename plat/marvell/armada/{a3700 => a3k}/a3700/plat_bl31_setup.c (100%)
rename plat/marvell/armada/{a3700 => a3k}/a3700/platform.mk (75%)
rename plat/marvell/armada/{a3700 => a3k}/common/a3700_common.mk (99%)
rename plat/marvell/armada/{a3700 => a3k}/common/a3700_ea.c (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/a3700_sip_svc.c (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/aarch64/a3700_common.c (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/aarch64/plat_helpers.S (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/dram_win.c (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/include/a3700_plat_def.h (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/include/a3700_pm.h (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/include/ddr_info.h (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/include/dram_win.h (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/include/io_addr_dec.h (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/include/plat_macros.S (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/include/platform_def.h (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/io_addr_dec.c (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/marvell_plat_config.c (100%)
rename plat/marvell/armada/{a3700 => a3k}/common/plat_pm.c (100%)
diff --git a/include/plat/marvell/armada/a3700/common/armada_common.h b/include/plat/marvell/armada/a3k/common/armada_common.h
similarity index 100%
rename from include/plat/marvell/armada/a3700/common/armada_common.h
rename to include/plat/marvell/armada/a3k/common/armada_common.h
diff --git a/include/plat/marvell/armada/a3700/common/board_marvell_def.h b/include/plat/marvell/armada/a3k/common/board_marvell_def.h
similarity index 100%
rename from include/plat/marvell/armada/a3700/common/board_marvell_def.h
rename to include/plat/marvell/armada/a3k/common/board_marvell_def.h
diff --git a/include/plat/marvell/armada/a3700/common/marvell_def.h b/include/plat/marvell/armada/a3k/common/marvell_def.h
similarity index 100%
rename from include/plat/marvell/armada/a3700/common/marvell_def.h
rename to include/plat/marvell/armada/a3k/common/marvell_def.h
diff --git a/include/plat/marvell/armada/a3700/common/plat_marvell.h b/include/plat/marvell/armada/a3k/common/plat_marvell.h
similarity index 100%
rename from include/plat/marvell/armada/a3700/common/plat_marvell.h
rename to include/plat/marvell/armada/a3k/common/plat_marvell.h
diff --git a/plat/marvell/armada/a3700/a3700/board/pm_src.c b/plat/marvell/armada/a3k/a3700/board/pm_src.c
similarity index 100%
rename from plat/marvell/armada/a3700/a3700/board/pm_src.c
rename to plat/marvell/armada/a3k/a3700/board/pm_src.c
diff --git a/plat/marvell/armada/a3700/a3700/mvebu_def.h b/plat/marvell/armada/a3k/a3700/mvebu_def.h
similarity index 100%
rename from plat/marvell/armada/a3700/a3700/mvebu_def.h
rename to plat/marvell/armada/a3k/a3700/mvebu_def.h
diff --git a/plat/marvell/armada/a3700/a3700/plat_bl31_setup.c b/plat/marvell/armada/a3k/a3700/plat_bl31_setup.c
similarity index 100%
rename from plat/marvell/armada/a3700/a3700/plat_bl31_setup.c
rename to plat/marvell/armada/a3k/a3700/plat_bl31_setup.c
diff --git a/plat/marvell/armada/a3700/a3700/platform.mk b/plat/marvell/armada/a3k/a3700/platform.mk
similarity index 75%
rename from plat/marvell/armada/a3700/a3700/platform.mk
rename to plat/marvell/armada/a3k/a3700/platform.mk
index bd9464aae..050af4199 100644
--- a/plat/marvell/armada/a3700/a3700/platform.mk
+++ b/plat/marvell/armada/a3k/a3700/platform.mk
@@ -5,6 +5,6 @@
# https://spdx.org/licenses
#
-include plat/marvell/armada/a3700/common/a3700_common.mk
+include plat/marvell/armada/a3k/common/a3700_common.mk
include plat/marvell/armada/common/marvell_common.mk
diff --git a/plat/marvell/armada/a3700/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
similarity index 99%
rename from plat/marvell/armada/a3700/common/a3700_common.mk
rename to plat/marvell/armada/a3k/common/a3700_common.mk
index 36865a896..996556719 100644
--- a/plat/marvell/armada/a3700/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -7,7 +7,7 @@
MARVELL_PLAT_BASE := plat/marvell/armada
MARVELL_PLAT_INCLUDE_BASE := include/plat/marvell/armada
-PLAT_FAMILY := a3700
+PLAT_FAMILY := a3k
PLAT_FAMILY_BASE := $(MARVELL_PLAT_BASE)/$(PLAT_FAMILY)
PLAT_INCLUDE_BASE := $(MARVELL_PLAT_INCLUDE_BASE)/$(PLAT_FAMILY)
PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common
diff --git a/plat/marvell/armada/a3700/common/a3700_ea.c b/plat/marvell/armada/a3k/common/a3700_ea.c
similarity index 100%
rename from plat/marvell/armada/a3700/common/a3700_ea.c
rename to plat/marvell/armada/a3k/common/a3700_ea.c
diff --git a/plat/marvell/armada/a3700/common/a3700_sip_svc.c b/plat/marvell/armada/a3k/common/a3700_sip_svc.c
similarity index 100%
rename from plat/marvell/armada/a3700/common/a3700_sip_svc.c
rename to plat/marvell/armada/a3k/common/a3700_sip_svc.c
diff --git a/plat/marvell/armada/a3700/common/aarch64/a3700_common.c b/plat/marvell/armada/a3k/common/aarch64/a3700_common.c
similarity index 100%
rename from plat/marvell/armada/a3700/common/aarch64/a3700_common.c
rename to plat/marvell/armada/a3k/common/aarch64/a3700_common.c
diff --git a/plat/marvell/armada/a3700/common/aarch64/plat_helpers.S b/plat/marvell/armada/a3k/common/aarch64/plat_helpers.S
similarity index 100%
rename from plat/marvell/armada/a3700/common/aarch64/plat_helpers.S
rename to plat/marvell/armada/a3k/common/aarch64/plat_helpers.S
diff --git a/plat/marvell/armada/a3700/common/dram_win.c b/plat/marvell/armada/a3k/common/dram_win.c
similarity index 100%
rename from plat/marvell/armada/a3700/common/dram_win.c
rename to plat/marvell/armada/a3k/common/dram_win.c
diff --git a/plat/marvell/armada/a3700/common/include/a3700_plat_def.h b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
similarity index 100%
rename from plat/marvell/armada/a3700/common/include/a3700_plat_def.h
rename to plat/marvell/armada/a3k/common/include/a3700_plat_def.h
diff --git a/plat/marvell/armada/a3700/common/include/a3700_pm.h b/plat/marvell/armada/a3k/common/include/a3700_pm.h
similarity index 100%
rename from plat/marvell/armada/a3700/common/include/a3700_pm.h
rename to plat/marvell/armada/a3k/common/include/a3700_pm.h
diff --git a/plat/marvell/armada/a3700/common/include/ddr_info.h b/plat/marvell/armada/a3k/common/include/ddr_info.h
similarity index 100%
rename from plat/marvell/armada/a3700/common/include/ddr_info.h
rename to plat/marvell/armada/a3k/common/include/ddr_info.h
diff --git a/plat/marvell/armada/a3700/common/include/dram_win.h b/plat/marvell/armada/a3k/common/include/dram_win.h
similarity index 100%
rename from plat/marvell/armada/a3700/common/include/dram_win.h
rename to plat/marvell/armada/a3k/common/include/dram_win.h
diff --git a/plat/marvell/armada/a3700/common/include/io_addr_dec.h b/plat/marvell/armada/a3k/common/include/io_addr_dec.h
similarity index 100%
rename from plat/marvell/armada/a3700/common/include/io_addr_dec.h
rename to plat/marvell/armada/a3k/common/include/io_addr_dec.h
diff --git a/plat/marvell/armada/a3700/common/include/plat_macros.S b/plat/marvell/armada/a3k/common/include/plat_macros.S
similarity index 100%
rename from plat/marvell/armada/a3700/common/include/plat_macros.S
rename to plat/marvell/armada/a3k/common/include/plat_macros.S
diff --git a/plat/marvell/armada/a3700/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
similarity index 100%
rename from plat/marvell/armada/a3700/common/include/platform_def.h
rename to plat/marvell/armada/a3k/common/include/platform_def.h
diff --git a/plat/marvell/armada/a3700/common/io_addr_dec.c b/plat/marvell/armada/a3k/common/io_addr_dec.c
similarity index 100%
rename from plat/marvell/armada/a3700/common/io_addr_dec.c
rename to plat/marvell/armada/a3k/common/io_addr_dec.c
diff --git a/plat/marvell/armada/a3700/common/marvell_plat_config.c b/plat/marvell/armada/a3k/common/marvell_plat_config.c
similarity index 100%
rename from plat/marvell/armada/a3700/common/marvell_plat_config.c
rename to plat/marvell/armada/a3k/common/marvell_plat_config.c
diff --git a/plat/marvell/armada/a3700/common/plat_pm.c b/plat/marvell/armada/a3k/common/plat_pm.c
similarity index 100%
rename from plat/marvell/armada/a3700/common/plat_pm.c
rename to plat/marvell/armada/a3k/common/plat_pm.c
From ed84fe88296e2ca7ed87af24bd82008d8843d3d7 Mon Sep 17 00:00:00 2001
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Date: Fri, 12 Apr 2019 12:56:07 +0200
Subject: [PATCH 02/15] plat: marvell: armada: configure amb for all CPs
Before this patch the configuration took place only for CP0 and CP1, but
since new platforms can contains up to 3 CPs update is required.
Change-Id: Iebd50bbe7b9772063e2c4efb3a7ecbfd593e950d
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
---
plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
index 09b8446fa..3b81814f9 100644
--- a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
@@ -75,10 +75,8 @@ static int bl2_plat_mmap_init(void)
mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
/* Open AMB bridge required for MG access */
- cp110_amb_init(MVEBU_CP_REGS_BASE(0));
-
- if (CP_COUNT == 2)
- cp110_amb_init(MVEBU_CP_REGS_BASE(1));
+ for (cp = 0; cp < CP_COUNT; cp++)
+ cp110_amb_init(MVEBU_CP_REGS_BASE(cp));
return 0;
}
From 8e8ec8cff7facb5c76ebf1af09e93fa25360a621 Mon Sep 17 00:00:00 2001
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Date: Fri, 8 Mar 2019 19:51:21 +0100
Subject: [PATCH 03/15] marvell: comphy: update rx_training procedure
1) Relay only on rx training, remove parts responsible for tx training
(trx training).
2) Add extra steps e.g. preconfigure FFE before starting training.
3) Remove some unnecessary steps like RRBS31 loopback setting which
shouldn't be relevant for tx_training.
Change-Id: Ib1e8567714f9ce33578186a262c339aa4b1c51f2
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
---
drivers/marvell/comphy/comphy-cp110.h | 56 ++++++--
drivers/marvell/comphy/phy-comphy-cp110.c | 148 ++++++++--------------
2 files changed, 97 insertions(+), 107 deletions(-)
diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h
index 6eb7fd0d2..3678c90fb 100644
--- a/drivers/marvell/comphy/comphy-cp110.h
+++ b/drivers/marvell/comphy/comphy-cp110.h
@@ -659,18 +659,32 @@
(0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET)
#define HPIPE_CDR_CONTROL_REG 0x418
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \
- (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET)
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
- (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
- (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
+#define HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET 0
+#define HPIPE_CRD_MIDPOINT_PHASE_OS_MASK \
+ (0x3f << HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET)
#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
+#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
+#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
+ (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
+#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
+#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
+ (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
+#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14
+#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \
+ (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET)
+
+
+#define HPIPE_CDR_CONTROL1_REG 0x41c
+#define HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF 12
+#define HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK \
+ (0xf << HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF)
+
+#define HPIPE_CDR_CONTROL2_REG 0x420
+#define HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF 12
+#define HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK \
+ (0xf << HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF)
#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
@@ -749,6 +763,30 @@
#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
+#define HPIPE_TRX0_REG 0x4cc /*in doc 0x133*4*/
+#define HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF 2
+#define HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK \
+ (0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF)
+#define HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF 0
+#define HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK \
+ (0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF)
+
+#define HPIPE_TRX_REG1 0x4d0 /*in doc 0x134*4*/
+#define HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF 3
+#define HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK \
+ (0x1 << HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF)
+#define HPIPE_TRX_REG1_SUMFTAP_EN_OFF 10
+#define HPIPE_TRX_REG1_SUMFTAP_EN_MASK \
+ (0x3f << HPIPE_TRX_REG1_SUMFTAP_EN_OFF)
+
+#define HPIPE_TRX_REG2 0x4d8 /*in doc 0x136*4*/
+#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF 11
+#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK \
+ (0x1f << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF)
+#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF 7
+#define HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK \
+ (0xf << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF)
+
#define HPIPE_G1_SETTING_5_REG 0x538
#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index b68208629..3313a42cb 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -2012,12 +2012,58 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
return ret;
}
+static void rx_pre_train(uint64_t comphy_base, uint8_t comphy_index)
+{
+ uintptr_t hpipe_addr;
+ uint32_t mask, data;
+
+ hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
+ comphy_index);
+
+ debug("rx_training preparation\n\n");
+
+ mask = HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK;
+ data = (0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF);
+ mask |= HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK;
+ data |= (0x0 << HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF);
+ reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask);
+
+
+ mask = HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
+ data = (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
+ mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK;
+ data |= (0x0 << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF);
+ reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask);
+
+ mask = HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK;
+ data = (0x1 << HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF);
+ reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
+
+ mask = HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK;
+ data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF);
+ reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask);
+
+ mask = HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK;
+ data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF);
+ reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask);
+
+ mask = HPIPE_CRD_MIDPOINT_PHASE_OS_MASK;
+ data = (0x0 << HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET);
+ reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
+
+ mask = HPIPE_TRX_REG1_SUMFTAP_EN_MASK;
+ data = (0x38 << HPIPE_TRX_REG1_SUMFTAP_EN_OFF);
+ mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
+ data |= (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
+ reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
+}
+
int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
uint8_t comphy_index)
{
uint32_t mask, data, timeout;
uint32_t g1_ffe_cap_sel, g1_ffe_res_sel, align90, g1_dfe_res;
- uintptr_t hpipe_addr, sd_ip_addr;
+ uintptr_t hpipe_addr;
uint8_t ap_nr, cp_nr;
@@ -2025,30 +2071,10 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
comphy_index);
- sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
- comphy_index);
debug_enter();
- debug("stage: RF Reset\n");
-
- /* Release from hard reset */
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- /* Wait 50ms - until band gap and ref clock ready */
- mdelay(50);
+ rx_pre_train(comphy_base, comphy_index);
debug("Preparation for rx_training\n\n");
@@ -2068,34 +2094,10 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
data = 0 << HPIPE_DFE_RES_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
- debug("PRBS31 loppback\n\n");
-
- /* Configure PRBS counters */
- mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
- data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_DATA_MASK;
- data = 0xc4 << HPIPE_PHY_TEST_DATA_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_EN_MASK;
- data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mdelay(10);
- debug("Enable TX/RX training\n\n");
+ debug("Enable RX training\n\n");
mask = HPIPE_TRX_RX_TRAIN_EN_MASK;
data = 0x1 << HPIPE_TRX_RX_TRAIN_EN_OFFSET;
- mask |= HPIPE_TRX_RX_ANA_IF_CLK_ENE_MASK;
- data |= 0x1 << HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET;
- mask |= HPIPE_TRX_TX_CTRL_CLK_EN_MASK;
- data |= 0x1 << HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET;
- mask |= HPIPE_TRX_UPDATE_THEN_HOLD_MASK;
- data |= 0x1 << HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET;
- mask |= HPIPE_TRX_TX_F0T_EO_BASED_MASK;
- data |= 0x1 << HPIPE_TRX_TX_F0T_EO_BASED_OFFSET;
reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
/* Check the result of RX training */
@@ -2180,21 +2182,9 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
data = 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
- /* Use the value from CAL_OS_PH_EXT */
- mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK;
- data = 1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG,
- data, mask);
-
- /* Update align90 */
- mask = HPIPE_CAL_OS_PH_EXT_MASK;
- data = align90 << HPIPE_CAL_OS_PH_EXT_OFFSET;
- reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG,
- data, mask);
-
/* Force DFE resolution (use gen table value) */
mask = HPIPE_DFE_RES_FORCE_MASK;
- data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
+ data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
/* 0x111-G1 DFE_Setting_4 */
@@ -2202,38 +2192,6 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
data = g1_dfe_res << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
- debug("PRBS31 loppback\n\n");
-
- mask = HPIPE_PHY_TEST_PT_TESTMODE_MASK;
- data = 0x1 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_OOB_0_REGISTER, data, mask);
-
- /* Configure PRBS counters */
- mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
- data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_DATA_MASK;
- data = 0xc4 << HPIPE_PHY_TEST_DATA_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_EN_MASK;
- data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- /* Reset PRBS error counter */
- mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
- data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
- data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_PT_TESTMODE_MASK;
- data = 0x1 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_OOB_0_REGISTER, data, mask);
-
printf("########################################################\n");
printf("# To use trained values update the ATF sources:\n");
printf("# plat/marvell/armada/a8k/<board_type>/board/phy-porting-layer.h ");
@@ -2252,12 +2210,6 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
printf("};\n\n");
printf("########################################################\n");
- /* check */
- debug("PRBS error counter[0x%lx] 0x%x\n\n",
- hpipe_addr + HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG,
- mmio_read_32(hpipe_addr +
- HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG));
-
rx_trainng_done[ap_nr][cp_nr][comphy_index] = 1;
return 0;
From 050eb19c7e1a9115fce31cac4283bf1ef12df3d1 Mon Sep 17 00:00:00 2001
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Date: Thu, 28 Mar 2019 13:02:42 +0100
Subject: [PATCH 04/15] marvell: comphy: initialize common phy selector for AP
mode
Configuring common phy selector which was missing for AP mode.
Change-Id: I15be1ba50b8aafe9094734abec139d72c18bb224
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
---
drivers/marvell/comphy/phy-comphy-cp110.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index 3313a42cb..2760f4603 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -209,8 +209,10 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base,
* as SFI1/XFI1 available only for CP115.
*/
if ((mode == COMPHY_SGMII_MODE ||
- mode == COMPHY_HS_SGMII_MODE ||
- mode == COMPHY_SFI_MODE || mode == COMPHY_XFI_MODE)
+ mode == COMPHY_HS_SGMII_MODE ||
+ mode == COMPHY_SFI_MODE ||
+ mode == COMPHY_XFI_MODE ||
+ mode == COMPHY_AP_MODE)
&& COMPHY_GET_ID(comphy_mode) == 1)
reg |= COMMON_SELECTOR_COMPHY4_PORT1 <<
comphy_offset;
@@ -2225,12 +2227,16 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
* the network registers like: MG, AP, MAC, PCS, Serdes etc.)
*/
static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base,
- uint8_t comphy_index)
+ uint8_t comphy_index,
+ uint32_t comphy_mode)
{
uint32_t mask, data;
uintptr_t comphy_addr = comphy_addr =
COMPHY_ADDR(comphy_base, comphy_index);
+ /* configure phy selector for XFI/SFI */
+ mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index,
+ comphy_mode);
debug_enter();
debug("stage: RFU configurations - hard reset comphy\n");
/* RFU configurations - hard reset comphy */
@@ -2323,7 +2329,8 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
comphy_mode);
break;
case (COMPHY_AP_MODE):
- err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index);
+ err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index,
+ comphy_mode);
break;
default:
ERROR("comphy%d: unsupported comphy mode\n", comphy_index);
From 814ce2f9ef9f35c1b33c07d08eea72c3f5322bf7 Mon Sep 17 00:00:00 2001
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Date: Thu, 28 Mar 2019 16:09:38 +0100
Subject: [PATCH 05/15] plat: marvell: a8k: extend includes to take advantage
of the phy_porting_layer
The phy porting layer uses defaults defined in
"phy-default-porting-layer.h" when board specific file
"phy-porting-layer.h" is not found. Because of the regression the board
specific directory was not included, therefore all boards used default
parameters.
Change-Id: I66e5e6eb8a39cca5aeeb4de6dab2ceddc39c1e31
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
---
plat/marvell/armada/a8k/common/a8k_common.mk | 1 +
1 file changed, 1 insertion(+)
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index 8731aa64b..dcbf9a66e 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -52,6 +52,7 @@ MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
plat/common/plat_gicv2.c
PLAT_INCLUDES := -I$(BOARD_DIR) \
+ -I$(BOARD_DIR)/board \
-I$(PLAT_COMMON_BASE)/include \
-I$(PLAT_INCLUDE_BASE)/common
From cdfbbfefcb485d68799249fe7d5585bd844ed17d Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Thu, 14 Mar 2019 17:24:40 +0200
Subject: [PATCH 06/15] plat: marvell: armada: re-enable BL32_BASE definition
As a preparation to support proper loading the OPTEE OS image,
enable the BL32 specific defines in case the SPD is used.
On the occasion move two BL32-related macros to marvell_def.h
and fix BL32_LIMIT definition.
Change-Id: Id4e2d81833bc1895650cca8b0fc0bfc341cf77f3
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
include/plat/marvell/armada/a3k/common/marvell_def.h | 10 ++++++++++
include/plat/marvell/armada/a8k/common/marvell_def.h | 9 +++++++++
plat/marvell/armada/a3k/common/include/platform_def.h | 8 --------
plat/marvell/armada/a8k/common/include/platform_def.h | 8 --------
4 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/include/plat/marvell/armada/a3k/common/marvell_def.h b/include/plat/marvell/armada/a3k/common/marvell_def.h
index eb13ba8af..3581a1c6e 100644
--- a/include/plat/marvell/armada/a3k/common/marvell_def.h
+++ b/include/plat/marvell/armada/a3k/common/marvell_def.h
@@ -173,5 +173,15 @@
#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
MARVELL_BL_RAM_SIZE)
+/*****************************************************************************
+ * BL32 specific defines.
+ *****************************************************************************
+ */
+#define BL32_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
+#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_DRAM_SIZE)
+
+#ifdef SPD_none
+#undef BL32_BASE
+#endif /* SPD_none */
#endif /* MARVELL_DEF_H */
diff --git a/include/plat/marvell/armada/a8k/common/marvell_def.h b/include/plat/marvell/armada/a8k/common/marvell_def.h
index 4eda01f1e..1a417db84 100644
--- a/include/plat/marvell/armada/a8k/common/marvell_def.h
+++ b/include/plat/marvell/armada/a8k/common/marvell_def.h
@@ -177,5 +177,14 @@
#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
MARVELL_BL_RAM_SIZE)
+/*******************************************************************************
+ * BL32 specific defines.
+ ******************************************************************************/
+#define BL32_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
+#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_DRAM_SIZE)
+
+#ifdef SPD_none
+#undef BL32_BASE
+#endif /* SPD_none */
#endif /* MARVELL_DEF_H */
diff --git a/plat/marvell/armada/a3k/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
index e6660d407..c20885553 100644
--- a/plat/marvell/armada/a3k/common/include/platform_def.h
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
@@ -221,12 +221,4 @@
/* Securities */
#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
-#define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
-#define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE
-
-#ifdef BL32
-#define BL32_BASE TRUSTED_DRAM_BASE
-#define BL32_LIMIT TRUSTED_DRAM_SIZE
-#endif
-
#endif /* PLATFORM_DEF_H */
diff --git a/plat/marvell/armada/a8k/common/include/platform_def.h b/plat/marvell/armada/a8k/common/include/platform_def.h
index ec1c9036c..06e781464 100644
--- a/plat/marvell/armada/a8k/common/include/platform_def.h
+++ b/plat/marvell/armada/a8k/common/include/platform_def.h
@@ -190,14 +190,6 @@
/* Securities */
#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
-#define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
-#define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE
-
-#ifdef BL32
-#define BL32_BASE TRUSTED_DRAM_BASE
-#define BL32_LIMIT TRUSTED_DRAM_SIZE
-#endif
-
#define MVEBU_PMU_IRQ_WA
#endif /* PLATFORM_DEF_H */
From e825176f1c499c6bedfe7eb887350a5e2ccbe239 Mon Sep 17 00:00:00 2001
From: Ben Peled <bpeled@marvell.com>
Date: Tue, 26 Mar 2019 19:06:24 +0200
Subject: [PATCH 07/15] plat: marvell: a8k: move address config of cp1/2 to BL2
The configuration space of each standalone CP was updated in BL31.
Loading FW procedure take places earlier in SCP_BL2.
It needs to be done after access to each CP is provided.
Moving the proper configuration from BL31 to BL2 solves it.
Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea
Signed-off-by: Ben Peled <bpeled@marvell.com>
---
.../armada/a8k/common/mss/mss_bl2_setup.c | 16 ++++++++++------
plat/marvell/armada/a8k/common/plat_bl31_setup.c | 9 ---------
2 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
index 3b81814f9..cdbae9df1 100644
--- a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
@@ -10,6 +10,7 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/marvell/ccu.h>
+#include <drivers/marvell/mochi/ap_setup.h>
#include <drivers/marvell/mochi/cp110_setup.h>
#include <lib/mmio.h>
@@ -18,9 +19,6 @@
#include "mss_scp_bootloader.h"
-/* IO windows configuration */
-#define IOW_GCR_OFFSET (0x70)
-
/* MSS windows configuration */
#define MSS_AEBR(base) (base + 0x160)
#define MSS_AIBR(base) (base + 0x164)
@@ -51,7 +49,7 @@ struct addr_map_win ccu_mem_map[] = {
*/
static int bl2_plat_mmap_init(void)
{
- int cfg_num, win_id, cfg_idx;
+ int cfg_num, win_id, cfg_idx, cp;
cfg_num = ARRAY_SIZE(ccu_mem_map);
@@ -71,8 +69,14 @@ static int bl2_plat_mmap_init(void)
ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
}
- /* Set the default target id to PIDI */
- mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
+ /* Config address for each cp other than cp0 */
+ for (cp = 1; cp < CP_COUNT; cp++)
+ update_cp110_default_win(cp);
+
+ /* There is need to configure IO_WIN windows again to overwrite
+ * temporary configuration done during update_cp110_default_win
+ */
+ init_io_win(MVEBU_AP0);
/* Open AMB bridge required for MG access */
for (cp = 0; cp < CP_COUNT; cp++)
diff --git a/plat/marvell/armada/a8k/common/plat_bl31_setup.c b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
index 621f43c63..552c9b298 100644
--- a/plat/marvell/armada/a8k/common/plat_bl31_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
@@ -116,21 +116,12 @@ void bl31_plat_arch_setup(void)
marvell_bl31_plat_arch_setup();
for (cp = 0; cp < CP_COUNT; cp++) {
- if (cp >= 1)
- update_cp110_default_win(cp);
-
cp110_init(MVEBU_CP_REGS_BASE(cp),
STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
marvell_bl31_mpp_init(cp);
}
- /*
- * There is need to configure IO_WIN windows again to overwrite
- * temporary configuration done during update_cp110_default_win
- */
- init_io_win(MVEBU_AP0);
-
for (cp = 1; cp < CP_COUNT; cp++)
mci_link_tune(cp - 1);
From 772aa5ba75f38930e8e9c3f370a4e2aa9f5f417c Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Mon, 25 Mar 2019 15:35:41 +0200
Subject: [PATCH 08/15] drivers: marvell: align and extend llc macros
Make all LLC-related macros to start with the same prefix
Add more LLC control registers definitions
This patch is a preparation step for LLC SRAM support
Change-Id: I0a4f0fc83e8ef35be93dd239a85f2a9f88d1ab19
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
drivers/marvell/cache_llc.c | 6 +++---
include/drivers/marvell/cache_llc.h | 19 ++++++++++++++-----
.../armada/common/aarch64/marvell_helpers.S | 2 +-
3 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/marvell/cache_llc.c b/drivers/marvell/cache_llc.c
index 3df93a43b..9b614c496 100644
--- a/drivers/marvell/cache_llc.c
+++ b/drivers/marvell/cache_llc.c
@@ -31,19 +31,19 @@ void llc_cache_sync(int ap_index)
void llc_flush_all(int ap_index)
{
- mmio_write_32(L2X0_CLEAN_INV_WAY(ap_index), LLC_WAY_MASK);
+ mmio_write_32(LLC_CLEAN_INV_WAY(ap_index), LLC_ALL_WAYS_MASK);
llc_cache_sync(ap_index);
}
void llc_clean_all(int ap_index)
{
- mmio_write_32(L2X0_CLEAN_WAY(ap_index), LLC_WAY_MASK);
+ mmio_write_32(LLC_CLEAN_WAY(ap_index), LLC_ALL_WAYS_MASK);
llc_cache_sync(ap_index);
}
void llc_inv_all(int ap_index)
{
- mmio_write_32(L2X0_INV_WAY(ap_index), LLC_WAY_MASK);
+ mmio_write_32(LLC_INV_WAY(ap_index), LLC_ALL_WAYS_MASK);
llc_cache_sync(ap_index);
}
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
index 85babb8d4..d8eca9fbf 100644
--- a/include/drivers/marvell/cache_llc.h
+++ b/include/drivers/marvell/cache_llc.h
@@ -14,18 +14,27 @@
#define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100)
#define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700)
-#define L2X0_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C)
-#define L2X0_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC)
-#define L2X0_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC)
+#define LLC_BANKED_MNT_AHR(ap) (MVEBU_LLC_BASE(ap) + 0x724)
+#define LLC_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C)
+#define LLC_BLK_ALOC(ap) (MVEBU_LLC_BASE(ap) + 0x78c)
+#define LLC_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC)
+#define LLC_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC)
#define LLC_TC0_LOCK(ap) (MVEBU_LLC_BASE(ap) + 0x920)
#define MASTER_LLC_CTRL LLC_CTRL(MVEBU_AP0)
-#define MASTER_L2X0_INV_WAY L2X0_INV_WAY(MVEBU_AP0)
+#define MASTER_LLC_INV_WAY LLC_INV_WAY(MVEBU_AP0)
#define MASTER_LLC_TC0_LOCK LLC_TC0_LOCK(MVEBU_AP0)
#define LLC_CTRL_EN 1
#define LLC_EXCLUSIVE_EN 0x100
-#define LLC_WAY_MASK 0xFFFFFFFF
+#define LLC_ALL_WAYS_MASK 0xFFFFFFFF
+
+/* AP806/AP807 - 1MB 8-ways LLC */
+#define LLC_WAYS 8
+#define LLC_WAY_MASK ((1 << LLC_WAYS) - 1)
+#define LLC_SIZE (1024 * 1024)
+#define LLC_WAY_SIZE (LLC_SIZE / LLC_WAYS)
+
#ifndef __ASSEMBLER__
void llc_cache_sync(int ap_index);
diff --git a/plat/marvell/armada/common/aarch64/marvell_helpers.S b/plat/marvell/armada/common/aarch64/marvell_helpers.S
index 6f625b95d..4ddc73db5 100644
--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
@@ -185,7 +185,7 @@ func disable_sram
/* Invalidate all ways */
ldr w1, =LLC_WAY_MASK
- ldr x0, =MASTER_L2X0_INV_WAY
+ ldr x0, =MASTER_LLC_INV_WAY
str w1, [x0]
/* Finally disable LLC */
From 957a5add638b1269210eac3a655e6b15e6fdb92e Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Sun, 31 Mar 2019 17:20:19 +0300
Subject: [PATCH 09/15] drivers: marvell: add CCU driver API for window state
checking
Add ccu_is_win_enabled() API for checking the CCU window
state using AP and window indexes.
Change-Id: Ib955a2cac28b2729b0a763f3bbbea28b476a2fe4
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
drivers/marvell/ccu.c | 10 ++++++++--
include/drivers/marvell/ccu.h | 1 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/marvell/ccu.c b/drivers/marvell/ccu.c
index 1e4ab44da..c73516eae 100644
--- a/drivers/marvell/ccu.c
+++ b/drivers/marvell/ccu.c
@@ -54,8 +54,8 @@ static void dump_ccu(int ap_index)
win_id));
start = ((uint64_t)alr << ADDRESS_SHIFT);
end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
- printf("\tccu %02x 0x%016llx 0x%016llx\n",
- target_id, start, end);
+ printf("\tccu%d %02x 0x%016llx 0x%016llx\n",
+ win_id, target_id, start, end);
}
}
win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index));
@@ -81,6 +81,12 @@ void ccu_win_check(struct addr_map_win *win)
}
}
+int ccu_is_win_enabled(int ap_index, uint32_t win_id)
+{
+ return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) &
+ WIN_ENABLE_BIT;
+}
+
void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id)
{
uint32_t ccu_win_reg;
diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h
index b0d1ec984..413ffb972 100644
--- a/include/drivers/marvell/ccu.h
+++ b/include/drivers/marvell/ccu.h
@@ -46,6 +46,7 @@ void ccu_dram_win_config(int ap_index, struct addr_map_win *win);
void ccu_dram_target_set(int ap_index, uint32_t target);
void ccu_save_win_all(int ap_id);
void ccu_restore_win_all(int ap_id);
+int ccu_is_win_enabled(int ap_index, uint32_t win_id);
#endif
#endif /* CCU_H */
From c96aa7fb3d9b306d50d71659a3c3d036ac9e3673 Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Sun, 31 Mar 2019 17:22:53 +0300
Subject: [PATCH 10/15] plat: marvell: armada: a8k: check CCU window state
before loading MSS BL2
Make sure the current CCU window is not in use before adding
a new address map during MSS BL2 image load preparations.
At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is
added to MSS BL2 stage initialization, the DDR entry will be destroyed
and lead to the system hang.
Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
index cdbae9df1..c2cd93357 100644
--- a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
@@ -63,10 +63,15 @@ static int bl2_plat_mmap_init(void)
* Do not touch CCU window 0,
* it's used for the internal registers access
*/
- for (cfg_idx = 0, win_id = 1; cfg_idx < cfg_num; cfg_idx++, win_id++) {
+ for (cfg_idx = 0, win_id = 1;
+ (win_id < MVEBU_CCU_MAX_WINS) && (cfg_idx < cfg_num); win_id++) {
+ /* Skip already enabled CCU windows */
+ if (ccu_is_win_enabled(MVEBU_AP0, win_id))
+ continue;
/* Enable required CCU windows */
ccu_win_check(&ccu_mem_map[cfg_idx]);
ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
+ cfg_idx++;
}
/* Config address for each cp other than cp0 */
From 63a0b12794ca38d0bdf8982ae4009b78350c43e5 Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Fri, 19 Jun 2020 17:48:48 +0200
Subject: [PATCH 11/15] plat: marvell: armada: platform definitions cleanup
- Remove
TRUSTED_DRAM_BASE
TRUSTED_DRAM_SIZE
MARVELL_TRUSTED_SRAM_BASE
- Rename
PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_*
PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_*
MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM
- Move
MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h
- Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map
- Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM
- Add minor style improvents
Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[Improve patch after rebase]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
.../armada/a3k/common/board_marvell_def.h | 2 --
.../marvell/armada/a3k/common/marvell_def.h | 15 +++++-----
.../armada/a8k/common/board_marvell_def.h | 3 --
.../marvell/armada/a8k/common/marvell_def.h | 30 ++++++++++++-------
.../armada/a3k/common/include/platform_def.h | 7 ++---
.../armada/a8k/common/aarch64/a8k_common.c | 8 +++--
.../armada/a8k/common/include/platform_def.h | 15 ++++++----
7 files changed, 45 insertions(+), 35 deletions(-)
diff --git a/include/plat/marvell/armada/a3k/common/board_marvell_def.h b/include/plat/marvell/armada/a3k/common/board_marvell_def.h
index 178259662..bc3e04f00 100644
--- a/include/plat/marvell/armada/a3k/common/board_marvell_def.h
+++ b/include/plat/marvell/armada/a3k/common/board_marvell_def.h
@@ -71,6 +71,4 @@
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
-#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */
-
#endif /* BOARD_MARVELL_DEF_H */
diff --git a/include/plat/marvell/armada/a3k/common/marvell_def.h b/include/plat/marvell/armada/a3k/common/marvell_def.h
index 3581a1c6e..1394c05ab 100644
--- a/include/plat/marvell/armada/a3k/common/marvell_def.h
+++ b/include/plat/marvell/armada/a3k/common/marvell_def.h
@@ -49,15 +49,17 @@
*/
#define MARVELL_LOCAL_STATE_OFF 2
+/* This leaves a gap between end of DRAM and start of ROM block */
+#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */
+
/* The first 4KB of Trusted SRAM are used as shared memory */
-#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
-#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
+#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE
#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
/* The remaining Trusted SRAM is used to load the BL images */
#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
MARVELL_SHARED_RAM_SIZE)
-#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
+#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \
MARVELL_SHARED_RAM_SIZE)
#define MARVELL_DRAM_BASE ULL(0x0)
@@ -65,7 +67,7 @@
#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \
MARVELL_DRAM_SIZE - 1)
-#define MARVELL_IRQ_SEC_PHY_TIMER 29
+#define MARVELL_IRQ_SEC_PHY_TIMER 29
#define MARVELL_IRQ_SEC_SGI_0 8
#define MARVELL_IRQ_SEC_SGI_1 9
@@ -86,7 +88,6 @@
MARVELL_DRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
@@ -177,8 +178,8 @@
* BL32 specific defines.
*****************************************************************************
*/
-#define BL32_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
-#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_DRAM_SIZE)
+#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
+#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE)
#ifdef SPD_none
#undef BL32_BASE
diff --git a/include/plat/marvell/armada/a8k/common/board_marvell_def.h b/include/plat/marvell/armada/a8k/common/board_marvell_def.h
index 0da56e7af..7e90f5f19 100644
--- a/include/plat/marvell/armada/a8k/common/board_marvell_def.h
+++ b/include/plat/marvell/armada/a8k/common/board_marvell_def.h
@@ -71,7 +71,4 @@
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
-#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */
-
-
#endif /* BOARD_MARVELL_DEF_H */
diff --git a/include/plat/marvell/armada/a8k/common/marvell_def.h b/include/plat/marvell/armada/a8k/common/marvell_def.h
index 1a417db84..9fd972597 100644
--- a/include/plat/marvell/armada/a8k/common/marvell_def.h
+++ b/include/plat/marvell/armada/a8k/common/marvell_def.h
@@ -47,15 +47,17 @@
*/
#define MARVELL_LOCAL_STATE_OFF 2
+/* This leaves a gap between end of DRAM and start of ROM block */
+#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */
+
/* The first 4KB of Trusted SRAM are used as shared memory */
-#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
-#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
+#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE
#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
/* The remaining Trusted SRAM is used to load the BL images */
#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
MARVELL_SHARED_RAM_SIZE)
-#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
+#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \
MARVELL_SHARED_RAM_SIZE)
/* Non-shared DRAM */
#define MARVELL_DRAM_BASE ULL(0x0)
@@ -75,17 +77,25 @@
#define MARVELL_IRQ_SEC_SGI_6 14
#define MARVELL_IRQ_SEC_SGI_7 15
-#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \
- MARVELL_SHARED_RAM_BASE,\
- MARVELL_SHARED_RAM_SIZE,\
+#if LLC_SRAM
+/* The entire LLC SRAM should be marked as secure in MMU tables,
+ * otherwise any access to it will produce exception
+ */
+#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \
+ PLAT_MARVELL_LLC_SRAM_BASE,\
+ PLAT_MARVELL_LLC_SRAM_SIZE,\
MT_MEMORY | MT_RW | MT_SECURE)
-
+#else
+#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \
+ MARVELL_SHARED_RAM_BASE, \
+ MARVELL_SHARED_RAM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif
#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
MARVELL_DRAM_BASE, \
MARVELL_DRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
@@ -180,8 +190,8 @@
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
-#define BL32_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
-#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_DRAM_SIZE)
+#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
+#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE)
#ifdef SPD_none
#undef BL32_BASE
diff --git a/plat/marvell/armada/a3k/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
index c20885553..ed1b3f7c8 100644
--- a/plat/marvell/armada/a3k/common/include/platform_def.h
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
@@ -84,8 +84,8 @@
/* 64 MB TODO: reduce this to minimum needed according to fip image size*/
#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
-#define PLAT_MARVELL_TRUSTED_DRAM_BASE 0x04400000
-#define PLAT_MARVELL_TRUSTED_DRAM_SIZE 0x01000000 /* 16 MB */
+#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
+#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x01000000 /* 16 MB */
/*
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
@@ -169,8 +169,7 @@
#define PLAT_MARVELL_NSTIMER_FRAME_ID 1
/* Mailbox base address */
-#define PLAT_MARVELL_MAILBOX_BASE \
- (MARVELL_TRUSTED_SRAM_BASE + 0x400)
+#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE + 0x400)
#define PLAT_MARVELL_MAILBOX_SIZE 0x100
#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
diff --git a/plat/marvell/armada/a8k/common/aarch64/a8k_common.c b/plat/marvell/armada/a8k/common/aarch64/a8k_common.c
index 7c2bf318f..a2e7402e6 100644
--- a/plat/marvell/armada/a8k/common/aarch64/a8k_common.c
+++ b/plat/marvell/armada/a8k/common/aarch64/a8k_common.c
@@ -18,14 +18,14 @@
*/
#if IMAGE_BL1
const mmap_region_t plat_marvell_mmap[] = {
- MARVELL_MAP_SHARED_RAM,
+ MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
{0}
};
#endif
#if IMAGE_BL2
const mmap_region_t plat_marvell_mmap[] = {
- MARVELL_MAP_SHARED_RAM,
+ MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
MARVELL_MAP_DRAM,
{0}
@@ -34,6 +34,7 @@ const mmap_region_t plat_marvell_mmap[] = {
#if IMAGE_BL2U
const mmap_region_t plat_marvell_mmap[] = {
+ MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
{0}
};
@@ -48,7 +49,7 @@ const mmap_region_t plat_marvell_mmap[] = {
#if IMAGE_BL31
const mmap_region_t plat_marvell_mmap[] = {
- MARVELL_MAP_SHARED_RAM,
+ MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
MARVELL_MAP_DRAM,
{0}
@@ -56,6 +57,7 @@ const mmap_region_t plat_marvell_mmap[] = {
#endif
#if IMAGE_BL32
const mmap_region_t plat_marvell_mmap[] = {
+ MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
{0}
};
diff --git a/plat/marvell/armada/a8k/common/include/platform_def.h b/plat/marvell/armada/a8k/common/include/platform_def.h
index 06e781464..d0df06271 100644
--- a/plat/marvell/armada/a8k/common/include/platform_def.h
+++ b/plat/marvell/armada/a8k/common/include/platform_def.h
@@ -92,13 +92,16 @@
#define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \
PLAT_MARVELL_CLUSTER_CORE_COUNT)
-/* DRAM[2MB..66MB] is used as Trusted ROM */
+/* Part of DRAM that is used as Trusted ROM */
#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
/* 64 MB TODO: reduce this to minimum needed according to fip image size */
#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
-/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
-#define PLAT_MARVELL_TRUSTED_DRAM_BASE 0x04400000
-#define PLAT_MARVELL_TRUSTED_DRAM_SIZE 0x01000000 /* 16 MB */
+/* Reserve 16M for SCP (Secure PayLoad) Trusted RAM */
+#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
+#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x01000000 /* 16 MB DRAM */
+
+#define PLAT_MARVELL_LLC_SRAM_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
+#define PLAT_MARVELL_LLC_SRAM_SIZE 0x00100000 /* 1 MB SRAM */
/*
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
@@ -182,8 +185,8 @@
/* Mailbox base address (note the lower memory space
* is reserved for BLE data)
*/
-#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE \
- + 0x400)
+#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE \
+ + 0x400)
#define PLAT_MARVELL_MAILBOX_SIZE 0x100
#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
From 94d6f48368d355406fc2f2e34333e905d7e6ea7c Mon Sep 17 00:00:00 2001
From: Marcin Wojtas <mw@semihalf.com>
Date: Fri, 19 Jun 2020 17:51:08 +0200
Subject: [PATCH 12/15] plat: marvell: armada: reduce memory size reserved for
FIP image
It is not needed to reserve 64MB for FIP. Limit this to 4MB
for both supported Armada SoC families.
Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[Extract from bigger commit]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
plat/marvell/armada/a3k/common/include/platform_def.h | 4 ++--
plat/marvell/armada/a8k/common/include/platform_def.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/plat/marvell/armada/a3k/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
index ed1b3f7c8..7f8f79a45 100644
--- a/plat/marvell/armada/a3k/common/include/platform_def.h
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
@@ -81,8 +81,8 @@
#define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2)
/* DRAM[2MB..66MB] is used as Trusted ROM */
#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
-/* 64 MB TODO: reduce this to minimum needed according to fip image size*/
-#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
+/* 4 MB for FIP image */
+#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000
/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x01000000 /* 16 MB */
diff --git a/plat/marvell/armada/a8k/common/include/platform_def.h b/plat/marvell/armada/a8k/common/include/platform_def.h
index d0df06271..b26e3ea1e 100644
--- a/plat/marvell/armada/a8k/common/include/platform_def.h
+++ b/plat/marvell/armada/a8k/common/include/platform_def.h
@@ -94,8 +94,8 @@
/* Part of DRAM that is used as Trusted ROM */
#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
-/* 64 MB TODO: reduce this to minimum needed according to fip image size */
-#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
+/* 4 MB for FIP image */
+#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000
/* Reserve 16M for SCP (Secure PayLoad) Trusted RAM */
#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x01000000 /* 16 MB DRAM */
From 85440805d46646871dc9b2934a0a3932b44df7d4 Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Sun, 31 Mar 2019 17:16:35 +0300
Subject: [PATCH 13/15] plat: marvell: armada: add LLC SRAM CCU setup for
AP806/AP807 platforms
Extend the CCU tables with secure SRAM window in all board
setups that uses SoCs based on AP806/AP807 North Bridges
Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c | 3 +++
plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c | 3 +++
plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c | 3 +++
.../marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c | 3 +++
4 files changed, 12 insertions(+)
diff --git a/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c
index d126f5567..7d30ebe5a 100644
--- a/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c
@@ -102,6 +102,9 @@ struct addr_map_win ccu_memory_map[] = { /* IO window */
#ifdef IMAGE_BLE
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
#else
+#if LLC_SRAM
+ {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
+#endif
{0x00000000f2000000, 0xe000000, IO_0_TID},
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
diff --git a/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c
index f8a1c40be..7fc33f1f9 100644
--- a/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c
@@ -93,6 +93,9 @@ struct addr_map_win ccu_memory_map[] = {
#ifdef IMAGE_BLE
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
#else
+#if LLC_SRAM
+ {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
+#endif
{0x00000000f2000000, 0xe000000, IO_0_TID},
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
{0x0000000800000000, 0x200000000, IO_0_TID}, /* IO window */
diff --git a/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c
index 7901dd225..856c07a6e 100644
--- a/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c
@@ -131,6 +131,9 @@ struct addr_map_win ccu_memory_map[] = {
#ifdef IMAGE_BLE
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
#else
+#if LLC_SRAM
+ {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
+#endif
{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
diff --git a/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c
index fa4e144c9..0edc97745 100644
--- a/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c
@@ -165,6 +165,9 @@ struct addr_map_win ccu_memory_map[] = {
#ifdef IMAGE_BLE
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
#else
+#if LLC_SRAM
+ {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
+#endif
{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
From 5a40d70f067b6238159142755e4e5cb27e292045 Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Sun, 31 Mar 2019 16:58:11 +0300
Subject: [PATCH 14/15] drivers: marvell: add support for mapping the entire
LLC to SRAM
Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - disabled
by the default.
Add description of LLC_SRAM flag to the build documentation.
Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
docs/plat/marvell/armada/build.rst | 7 ++++
drivers/marvell/cache_llc.c | 38 ++++++++++++++++++++
include/drivers/marvell/cache_llc.h | 17 +++++++--
plat/marvell/armada/common/marvell_common.mk | 13 +++++++
4 files changed, 72 insertions(+), 3 deletions(-)
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index 6f28721d5..bec0bcbd4 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -77,6 +77,13 @@ There are several build options:
Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``).
+- LLC_SRAM
+
+ Flag defining the LLC (L3) cache SRAM support. The feature is
+ disabled by default (``LLC_ENABLE=0``).
+ When LLC SRAM is enabled, the secure payload (BL32) is loaded into this
+ SRAM area instead of the DRAM.
+
- MARVELL_SECURE_BOOT
Build trusted(=1)/non trusted(=0) image, default is non trusted.
diff --git a/drivers/marvell/cache_llc.c b/drivers/marvell/cache_llc.c
index 9b614c496..836aae7b8 100644
--- a/drivers/marvell/cache_llc.c
+++ b/drivers/marvell/cache_llc.c
@@ -109,3 +109,41 @@ void llc_runtime_enable(int ap_index)
reg |= (0x1 << CCU_SET_POC_OFFSET);
mmio_write_32(CCU_HTC_CR(ap_index), reg);
}
+
+#if LLC_SRAM
+void llc_sram_enable(int ap_index)
+{
+ uint32_t tc, way;
+ uint32_t way_addr;
+
+ /* Lockdown all available ways for all traffic classes */
+ for (tc = 0; tc < LLC_TC_NUM; tc++)
+ mmio_write_32(LLC_TCN_LOCK(ap_index, tc), LLC_WAY_MASK);
+
+ /* Clear the high bits of SRAM address */
+ mmio_write_32(LLC_BANKED_MNT_AHR(ap_index), 0);
+
+ way_addr = PLAT_MARVELL_TRUSTED_RAM_BASE;
+ for (way = 0; way < LLC_WAYS; way++) {
+ /* Trigger allocation block command */
+ mmio_write_32(LLC_BLK_ALOC(ap_index),
+ LLC_BLK_ALOC_BASE_ADDR(way_addr) |
+ LLC_BLK_ALOC_WAY_DATA_CLR |
+ LLC_BLK_ALOC_WAY_ID(way));
+ way_addr += LLC_WAY_SIZE;
+ }
+ llc_enable(ap_index, 1);
+}
+
+void llc_sram_disable(int ap_index)
+{
+ uint32_t tc;
+
+ /* Disable the line lockings */
+ for (tc = 0; tc < LLC_TC_NUM; tc++)
+ mmio_write_32(LLC_TCN_LOCK(ap_index, tc), 0);
+
+ /* Invalidate all ways */
+ llc_inv_all(ap_index);
+}
+#endif /* LLC_SRAM */
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
index d8eca9fbf..b326474ee 100644
--- a/include/drivers/marvell/cache_llc.h
+++ b/include/drivers/marvell/cache_llc.h
@@ -13,17 +13,18 @@
#define CACHE_LLC_H
#define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100)
+#define LLC_SECURE_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x10C)
#define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700)
#define LLC_BANKED_MNT_AHR(ap) (MVEBU_LLC_BASE(ap) + 0x724)
#define LLC_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C)
#define LLC_BLK_ALOC(ap) (MVEBU_LLC_BASE(ap) + 0x78c)
#define LLC_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC)
#define LLC_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC)
-#define LLC_TC0_LOCK(ap) (MVEBU_LLC_BASE(ap) + 0x920)
+#define LLC_TCN_LOCK(ap, tc) (MVEBU_LLC_BASE(ap) + 0x920 + 4 * (tc))
#define MASTER_LLC_CTRL LLC_CTRL(MVEBU_AP0)
#define MASTER_LLC_INV_WAY LLC_INV_WAY(MVEBU_AP0)
-#define MASTER_LLC_TC0_LOCK LLC_TC0_LOCK(MVEBU_AP0)
+#define MASTER_LLC_TC0_LOCK LLC_TCN_LOCK(MVEBU_AP0, 0)
#define LLC_CTRL_EN 1
#define LLC_EXCLUSIVE_EN 0x100
@@ -34,7 +35,13 @@
#define LLC_WAY_MASK ((1 << LLC_WAYS) - 1)
#define LLC_SIZE (1024 * 1024)
#define LLC_WAY_SIZE (LLC_SIZE / LLC_WAYS)
+#define LLC_TC_NUM 15
+#define LLC_BLK_ALOC_WAY_ID(way) ((way) & 0x1f)
+#define LLC_BLK_ALOC_WAY_DATA_DSBL (0x0 << 6)
+#define LLC_BLK_ALOC_WAY_DATA_CLR (0x1 << 6)
+#define LLC_BLK_ALOC_WAY_DATA_SET (0x3 << 6)
+#define LLC_BLK_ALOC_BASE_ADDR(addr) ((addr) & (LLC_WAY_SIZE - 1))
#ifndef __ASSEMBLER__
void llc_cache_sync(int ap_index);
@@ -45,6 +52,10 @@ void llc_disable(int ap_index);
void llc_enable(int ap_index, int excl_mode);
int llc_is_exclusive(int ap_index);
void llc_runtime_enable(int ap_index);
-#endif
+#if LLC_SRAM
+void llc_sram_enable(int ap_index);
+void llc_sram_disable(int ap_index);
+#endif /* LLC_SRAM */
+#endif /* __ASSEMBLY__ */
#endif /* CACHE_LLC_H */
diff --git a/plat/marvell/armada/common/marvell_common.mk b/plat/marvell/armada/common/marvell_common.mk
index f5f0c416e..fcc97acd3 100644
--- a/plat/marvell/armada/common/marvell_common.mk
+++ b/plat/marvell/armada/common/marvell_common.mk
@@ -16,8 +16,21 @@ SEPARATE_CODE_AND_RODATA := 1
# flag to switch from PLL to ARO
ARO_ENABLE := 0
$(eval $(call add_define,ARO_ENABLE))
+
+# Convert LLC to secure SRAM
+LLC_SRAM := 0
+$(eval $(call add_define,LLC_SRAM))
+
# Enable/Disable LLC
+ifeq (${LLC_SRAM}, 0)
LLC_ENABLE := 1
+else
+# When LLC_SRAM=1, the entire LLC converted to SRAM and enabled at BL1.
+# All existing cases activating LLC at BL31 stage should be disabled.
+# The below assignment does not allow changing the LLC_ENABLE
+# value in the command line.
+LLC_ENABLE = 0
+endif
$(eval $(call add_define,LLC_ENABLE))
include lib/xlat_tables_v2/xlat_tables.mk
From 47d1773f90c84065c939ee190bb85f6221cd9dda Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Mon, 15 Apr 2019 16:29:08 +0300
Subject: [PATCH 15/15] plat: marvell: armada: a8k: add OP-TEE OS MMU tables
Adjust the latest OP-TEE memory definitions to the
newest TF-A baseline.
Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
.../marvell/armada/a8k/common/marvell_def.h | 38 +++++++++++++++----
.../armada/a8k/common/aarch64/a8k_common.c | 4 ++
2 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/include/plat/marvell/armada/a8k/common/marvell_def.h b/include/plat/marvell/armada/a8k/common/marvell_def.h
index 9fd972597..1245b88a2 100644
--- a/include/plat/marvell/armada/a8k/common/marvell_def.h
+++ b/include/plat/marvell/armada/a8k/common/marvell_def.h
@@ -77,20 +77,42 @@
#define MARVELL_IRQ_SEC_SGI_6 14
#define MARVELL_IRQ_SEC_SGI_7 15
-#if LLC_SRAM
-/* The entire LLC SRAM should be marked as secure in MMU tables,
- * otherwise any access to it will produce exception
+#ifdef SPD_opteed
+/*
+ * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
+ * load/authenticate the trusted os extra image. The first 512KB of
+ * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
+ * for OPTEE is paged image which only include the paging part using
+ * virtual memory but without "init" data. OPTEE will copy the "init" data
+ * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
+ * extra image behind the "init" data.
*/
-#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \
- PLAT_MARVELL_LLC_SRAM_BASE,\
- PLAT_MARVELL_LLC_SRAM_SIZE,\
+#define MARVELL_OPTEE_PAGEABLE_LOAD_BASE \
+ (PLAT_MARVELL_TRUSTED_RAM_BASE + \
+ PLAT_MARVELL_TRUSTED_RAM_SIZE - \
+ MARVELL_OPTEE_PAGEABLE_LOAD_SIZE)
+#define MARVELL_OPTEE_PAGEABLE_LOAD_SIZE 0x400000
+#define MARVELL_OPTEE_PAGEABLE_LOAD_MEM \
+ MAP_REGION_FLAT( \
+ MARVELL_OPTEE_PAGEABLE_LOAD_BASE, \
+ MARVELL_OPTEE_PAGEABLE_LOAD_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+/*
+ * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
+ * support is enabled).
+ */
+#define MARVELL_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
+ BL32_BASE, \
+ BL32_LIMIT - BL32_BASE, \
MT_MEMORY | MT_RW | MT_SECURE)
-#else
+#endif /* SPD_opteed */
+
#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \
MARVELL_SHARED_RAM_BASE, \
MARVELL_SHARED_RAM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
-#endif
+
#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
MARVELL_DRAM_BASE, \
MARVELL_DRAM_SIZE, \
diff --git a/plat/marvell/armada/a8k/common/aarch64/a8k_common.c b/plat/marvell/armada/a8k/common/aarch64/a8k_common.c
index a2e7402e6..4332a76ea 100644
--- a/plat/marvell/armada/a8k/common/aarch64/a8k_common.c
+++ b/plat/marvell/armada/a8k/common/aarch64/a8k_common.c
@@ -28,6 +28,10 @@ const mmap_region_t plat_marvell_mmap[] = {
MARVELL_MAP_SECURE_RAM,
MAP_DEVICE0,
MARVELL_MAP_DRAM,
+#ifdef SPD_opteed
+ MARVELL_MAP_OPTEE_CORE_MEM,
+ MARVELL_OPTEE_PAGEABLE_LOAD_MEM,
+#endif
{0}
};
#endif