Fixes a dangling pointer bug in `spmc_ffa_console_log`.
`chars` was assigned to an array which went out of scope at the end of
the `if`/`else` block.
The solution is to `memcmpy` from the temporary array into `chars`,
which is now an array.
Signed-off-by: Karl Meakin <karl.meakin@arm.com>
Change-Id: I67d19ea25d09b72f38fcc67dab4acf449aa8f1b1
A normal world caller can emit an SMC with the SVE hint bit set such
that the callee can perform an optimization by omitting to save/restore
the SVE context. Update the SPMD to pass this information to the SPMC
when set by the caller in the SMC flags parameter.
For now, restrict this behavior to the SPMC living at S-EL2.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icf46eb8a391dd3ddd2ee6aff8581a2f1c8a1c274
The toolchain refactor change introduces the `${toolchain}-${tool}-id`
variables, which provide identifiers for all of the toolchain tools used
by the build system. This change replaces the various conditions that
are in use to identify these tools based on the path with a standard set
of comparisons against these new identifier variables.
Change-Id: Ib60e592359fa6e415c19a012e68d660f87436ca7
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change migrates the values of `CC`, `CPP`, `AS` and other toolchain
variables to the new `$(toolchain)-$(tool)` variables, which were
introduced by the toolchain refactor patch. These variables should be
equivalent to the values that they're replacing.
Change-Id: I644fe4ce82ef1894bed129ddb4b6ab94fb04985d
Signed-off-by: Chris Kay <chris.kay@arm.com>
Added SiP calls to FVP platform to protect/unprotect a
memory range.
These leverage rme features to change the PAS of a given
memory range from non-secure to secure.
The mentioned call is leveraged by the SPMC in the memory
sharing flow, when memory is shared from the normal world
onto the secure world.
More details in the SPM related patches.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Iaf15d8603a549d247ffb1fc14c16bfb94d0e178a
Cortex-A715 erratum 2561034 is a Cat B erratum that applies to
revision r1p0 and is fixed in r1p1.
The workaround is to set bit[26] in CPUACTLR2_EL1. Setting this
bit is not expected to have a significant performance impact.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest
Change-Id: I377f250a2994b6ced3ac7d93f947af6ceb690d49
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
The ChromeOS will use the SMC to pass some secrets from firmware to
optee.
Change-Id: Iaf3357d40a7ed22415926acd9d7979df24dd81f1
Signed-off-by: Yi Chou <yich@google.com>
Cortex X3 erratum 2641945 is a Cat B erratum that applies to all
revisions <= r1p0 and is fixed in r1p1.
The workaround is to disable the affected L1 data cache prefetcher
by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance
penalty of ~1%. Contact Arm for an alternate workaround that impacts
power.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Currently CTX_INCLUDE_MTE_REGS is used for dual purpose,
to enable allocation tags register and to context save and restore
them and also to check if mte feature is available.
To make it more meaningful, remove CTX_INCLUDE_MTE_REGS
and introduce FEAT_MTE. This would enable allocation tags register
when FEAT_MTE is enabled and also supported from platform.
Also arch features can be conditionally enabled disabled based on
arch version from `make_helpers/arch_features.mk`
Change-Id: Ibdd2d43874634ad7ddff93c7edad6044ae1631ed
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Add handling for FF-A 1.2 FFA_MSG_SEND_DIR_REQ2 interface.
Handler validates security states of sender/receiver pairs
and forwards the call to other world if necessary.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I02a60362d8d9a50fcc0b6a84753cba274ba5eb1b
Cortex-A78C erratum 2683027 is a cat B erratum that applies to
revisions r0p1 - r0p2 and is still open. The workaround is to
execute a specific code sequence in EL3 during reset.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2004089/latest
Change-Id: I2bf9e675f48b62b4cd203100f7df40f4846aafa8
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Cortex-X3 erratum 2266875 is a Cat B erratum that applies to
all revisions <= r1p0 and is fixed in r1p1. The workaround is to
set CPUACTLR_EL1[22]=1 which will cause the CFP instruction to
invalidate all branch predictor resources regardless of context.
SDEN Documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I9c610777e222f57f520d223bb03fc5ad05af1077
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Cortex-X3 erratum 2302506 is a cat B erratum that applies to
revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to
set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave
like PLD/PRFM LD and not cause invalidation to other PE caches.
There might be a small performance degradation to this workaround
for certain workloads that share data.
SDEN can be found here:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I048b830867915b88afa36582c6da05734a56d22a
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Enable handoff to OP-TEE using transfer list.
Create transfer list when loading OP-TEE image via non-secure SMC call.
Fallback to default handoff args when transfer list is disabled or
transfer list signature does not exist.
Change-Id: I94bb5b7fdfbb8829016a9d5d9ef5aff993d7cc99
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Add support for FFA_CONSOLE_LOG in EL3 SPMC,
Disallow forwarding FFA_CONSOLE_LOG across worlds.
Add support for FFA_CONSOLE_LOG in FFA_FEATURES.
Input parameters:
w0/x0 - FFA_CONSOLE_LOG_32/64
w1/x1 - Character count
w2/x2-w7/x7 - 24 or 48 characters depending upon whether a SMC32 or
SMC64 FID was used.
Output parameters in case of success:
w0/x0 - FFA_SUCCESS
Output parameters in case of error:
w0/x0 - FFA_ERROR
w2/x2 - NOT_SUPPORTED: ABI is not implemented
INVALID_PARAMETERS: Parameters are incorrectly encoded
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I004c043729e77d1b9aa396c42d25c73d9268169a
The Test Realm Package (TRP) is a small payload that runs at R-EL2 if an
external RMM image path is not provided. Currently, the TRP makefile is
included if RME is enabled, regardless of whether an external RMM
image path is defined or not. This fix ensures that TRP is included
only when an external RMM path is not defined.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I3cc3d2a636e65071e45c5c82cc125290887ffc09
Cortex X3 erratum 2743088 is a Cat B erratum that applies to all
revisions <= r1p1 and is fixed in r1p2. The workaround is to add a DSB
instruction before the ISB of the powerdown code sequence specified in
the TRM.
SDEN documentation: https://developer.arm.com/documentation/2055130
Change-Id: I2c8577e3ca0781af8b1c3912e577d3bd77f92709
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Currently, the registers which are maintained per-world, does not
take into account the reset value while configuring the context for
the respective world.
This leads to an issue, wherein the register retains the same value
across world switch, which is an error.
This patch addresses this problem, by configuring the register
(cptr_el3) precisely according to the world, the cpu is in
execution via resetting it before initializing the world specific context.
Change-Id: I592d82af373155fca67eed109c199341c305f0b9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUACTLR_EL1.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5a07163f919352583b03328abd5659bf7b268677
Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest
Change-Id: Idb6f32f680ee1378a57c2d2f809ea847fffe5910
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Cortex-X2 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set CPUACTLR3_EL1[47] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest
Change-Id: Ia95f0e276482283bf50e06c58c2bc5faab3f62c6
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Cortex-A710 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set CPUACTLR3_EL1[47] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: Id3bb4a2673e41ff237682e46784d37752daf2f83
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Add support to setup S-EL0 SP context during power management power on
procedure. In case of power on, initialise the context data structure
for the secure world on the current CPU.
The S-EL0 SP does not support power message. Add the check to make
sure that it does not subscribe to any power messages.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Ic9cf98cd15b6ee5d86d071a52bc0973677049df3
* changes:
feat(rdn2): add dts for secure partition
feat(el3-spmc): synchronize access to the s-el0 sp context
feat(el3-spmc): add support to map S-EL0 SP device regions
feat(el3-spmc): add support to map S-EL0 SP memory regions
feat(el3-spmc): add support for FFA_MEM_PERM_GET and SET ABIs
feat(el3-spmc): add support to setup S-EL0 context
Neoverse V2 erratum 2618597 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
disable the use of the Full Retention power mode in the core (setting
WFI_RET_CTRL and WFE_RET_CTRL in IMP_CPUPWRCTLR_EL1 to 0b000).
SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2332927/latest
Change-Id: I23a81275d1e40cae39e6897093d6cdd3e11c08ea
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
This patch locks and unlocks access to the S-EL0 SP context when its
runtime state and model are updated to avoid issues around concurrent
access to global state.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I427657050574c189cbaf82c1371e3ee44bc1663e
Add the support to parse SP manifest to get device regions, create xlat
table entries for the SP.
SP running at SEL-0 does not have enough privilege to map the regions
itself.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I600f51ee62a33443fe7f1c4e007cc6c5ab45222f
Add the support to parse SP manifest to get memory regions, create xlat
tables and then program it in TTBR0.
SP manifest contains the info on memory map regions that are needed by
the SP. These regions needs to be mapped as SP running at S-EL0 does not
have privilege to do it.
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I0cad36e5c43f8a68c94887ff2bd798933a26be27
Secure partition running at SEL0 does not have privilege to modify
translation tables. So it needs SPMC to map the regions for it. Add the
support to request memory map or region info using FF-A interface.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Change-Id: I04a97899808bbd45eda24edf7bc74eaef96fb2ce
Add support to setup S-EL0 context by setting up the following
S-EL1 shim exception handlers: This is a trampoline between S-EL0 and
monitor running at EL3 and is used to
handle or forward exceptions from S-EL0.
Boot Info region: This region holds the boot protocol data that is
passed between SPMC and SP.
Setup system registers: Setup sctlr_el1, vbar_el1, cntkctl_el1,
ctx_cpacr_el1(enable fp and smid), spsr and
sp_el0
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I82d21fcd95529f235bee8bf838d36a2ac519bb0a
Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size statically to it's full size.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest
Change-Id: I3bc43e7299c17db8a6771a547515ffb2a172fa0f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2004089/latest
Change-Id: Ic62579c2dd69b7a8cbbeaa936f45b2cc9436439a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[61] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest
Change-Id: Ica402494f78811c85e56a262e1f60b09915168fe
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUACTLR3_EL1[47], this might have a small
impact on power and has negligible impact on performance.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: Id92dbae6f1f313b133ffaa018fbf9c078da55d75
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
There are various SMC calls which pass mpidr as an argument which is
currently tested at random places in SMC call path.
To make the mpidr validation check consistent across SMC calls, do
this check as part of SMC argument validation.
This patch introduce a helper function is_valid_mpidr() to validate
mpidr and call it as part of validating SMC arguments at starting of
SMC handlers (which expect mpidr as an argument).
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I11ea50e22caf17896cf4b2059b87029b2ba136b1
Enable SME for RMM using sme_enable_per_world as well as sme_enable.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I6070f4778e507ac9cbc7442e727bedad9b40e635
