fix(cpus): workaround for Cortex-A520 erratum 2630792

Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest

Change-Id: Idb6f32f680ee1378a57c2d2f809ea847fffe5910
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

docs/design/cpu-specific-build-macros.rst

@@ -840,6 +840,12 @@ For Cortex-A510, the following errata build flags are defined :
    Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
    r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3.
 
+For Cortex-A520, the following errata build flags are defined :
+
+-  ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to
+   Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the
+   CPU and is still open.
+
 For Cortex-A715, the following errata build flags are defined :
 
 -  ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715

include/lib/cpus/aarch64/cortex_a520.h

@@ -14,6 +14,11 @@
  ******************************************************************************/
 #define CORTEX_A520_CPUECTLR_EL1				S3_0_C15_C1_4
 
+/*******************************************************************************
+ * CPU Auxiliary Control register 1 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A520_CPUACTLR_EL1				S3_0_C15_C1_0
+
 /*******************************************************************************
  * CPU Power Control register specific definitions
  ******************************************************************************/

lib/cpus/aarch64/cortex_a520.S

@@ -21,6 +21,11 @@
 #error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
+workaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792
+	sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(38)
+workaround_reset_end cortex_a520, ERRATUM(2630792)
+
+check_erratum_ls cortex_a520, ERRATUM(2630792), CPU_REV(0, 1)
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------

lib/cpus/cpu-ops.mk

@@ -843,6 +843,10 @@ CPU_FLAG_LIST += ERRATA_A510_2666669
 # Cortex-A510 cpu and is fixed in r1p3.
 CPU_FLAG_LIST += ERRATA_A510_2684597
 
+# Flag to apply erratum 2630792 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1 of the Cortex-A520 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_A520_2630792
+
 # Flag to apply erratum 2331132 workaround during reset. This erratum applies
 # to revisions r0p0, r0p1 and r0p2. It is still open.
 CPU_FLAG_LIST += ERRATA_V2_2331132

services/std_svc/errata_abi/errata_abi_main.c

@@ -454,6 +454,17 @@ struct em_cpu_list cpu_list[] = {
 	}
 },
 #endif /* CORTEX_X3_H_INC */
+
+#if CORTEX_A520_H_INC
+{
+	.cpu_partnumber = CORTEX_A520_MIDR,
+	.cpu_errata_list = {
+		[0] = {2630792, 0x00, 0x01, ERRATA_A520_2630792},
+		[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+	}
+},
+#endif /* CORTEX_A520_H_INC */
+
 };
 
 /*