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Merge changes from topic "errata" into integration
* changes: fix(cpus): workaround for Cortex-A78C erratum 2683027 fix(cpus): workaround for Cortex-X3 erratum 2266875 fix(cpus): workaround for Cortex-X3 erratum 2302506
This commit is contained in:
Lauren Wehrmeister
TrustedFirmware Code Review
commit
3f02459572
6 changed files with 74 additions and 17 deletions
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@ -384,6 +384,10 @@ For Cortex-A78C, the following errata build flags are defined :
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Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
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erratum is still open.
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- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to
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Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
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erratum is still open.
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- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to
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Cortex-A78C CPU, this erratum affects system configurations that do not use
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an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2
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@ -771,6 +775,14 @@ For Cortex-X3, the following errata build flags are defined :
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CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of
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the CPU and is still open.
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- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3
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CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
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is fixed in r1p1.
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- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3
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CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is
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fixed in r1p2.
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- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to
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Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
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of the CPU, it is fixed in r1p1.
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@ -946,7 +958,7 @@ GIC Errata Workarounds
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--------------
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*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.*
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*Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.*
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.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
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.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -25,6 +25,11 @@
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#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4)
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#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR_EL1 S3_0_C15_C1_0
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -72,6 +72,19 @@ workaround_reset_end cortex_a78c, ERRATUM(2395411)
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check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
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workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027
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ldr x0, =0x3
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msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
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ldr x0, =0xEE010F10
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msr CORTEX_A78C_IMP_CPUPOR_EL3, x0
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ldr x0, =0xFF1F0FFE
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msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
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ldr x0, =0x100000004003FF
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msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
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workaround_reset_end cortex_a78c, ERRATUM(2683027)
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check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2)
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workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232
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/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
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sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -33,6 +33,18 @@ workaround_reset_end cortex_x3, ERRATUM(2070301)
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check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2)
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workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875
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sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22)
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workaround_reset_end cortex_x3, ERRATUM(2266875)
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check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0)
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workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506
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sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0)
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workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB
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check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1)
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workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
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sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
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workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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@ -388,6 +388,10 @@ CPU_FLAG_LIST += ERRATA_A78C_2376749
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# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
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CPU_FLAG_LIST += ERRATA_A78C_2395411
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# Flag to apply erratum 2683027 workaround during reset. This erratum applies
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# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
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CPU_FLAG_LIST += ERRATA_A78C_2683027
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# Flag to apply erratum 2712575 workaround for non-arm interconnect ip. This
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# erratum applies to revisions r0p1 and r0p2 of the A78C cpu.
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# It is still open.
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@ -774,6 +778,14 @@ CPU_FLAG_LIST += ERRATA_X2_2778471
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# still open.
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CPU_FLAG_LIST += ERRATA_X3_2070301
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# Flag to apply erratum 2266875 workaround during reset. This erratum applies
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# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
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CPU_FLAG_LIST += ERRATA_X3_2266875
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# Flag to apply erratum 2302506 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
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CPU_FLAG_LIST += ERRATA_X3_2302506
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# Flag to apply erratum 2313909 workaround on powerdown. This erratum applies
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# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
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CPU_FLAG_LIST += ERRATA_X3_2313909
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -237,12 +237,13 @@ struct em_cpu_list cpu_list[] = {
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[3] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638},
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[4] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749},
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[5] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
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[6] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
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[6] = {2683027, 0x01, 0x02, ERRATA_A78C_2683027},
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[7] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
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ERRATA_NON_ARM_INTERCONNECT},
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[7] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232},
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[8] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
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[9] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
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[10 ... ERRATA_LIST_END] = UNDEF_ERRATA,
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[8] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232},
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[9] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
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[10] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
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[11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
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}
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},
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#endif /* CORTEX_A78C_H_INC */
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@ -446,12 +447,14 @@ struct em_cpu_list cpu_list[] = {
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.cpu_partnumber = CORTEX_X3_MIDR,
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.cpu_errata_list = {
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[0] = {2070301, 0x00, 0x12, ERRATA_X3_2070301},
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[1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
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[2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
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[3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
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[4] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
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[5] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
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[6 ... ERRATA_LIST_END] = UNDEF_ERRATA,
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[1] = {2266875, 0x00, 0x10, ERRATA_X3_2266875},
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[2] = {2302506, 0x00, 0x11, ERRATA_X3_2302506},
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[3] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
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[4] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
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[5] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
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[6] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
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[7] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
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[8 ... ERRATA_LIST_END] = UNDEF_ERRATA,
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}
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},
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#endif /* CORTEX_X3_H_INC */
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