diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 905b0161f..3485dc910 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -384,6 +384,10 @@ For Cortex-A78C, the following errata build flags are defined : Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This erratum is still open. +- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to + Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This + erratum is still open. + - ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to Cortex-A78C CPU, this erratum affects system configurations that do not use an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 @@ -771,6 +775,14 @@ For Cortex-X3, the following errata build flags are defined : CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of the CPU and is still open. +- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 + CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it + is fixed in r1p1. + +- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 + CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is + fixed in r1p2. + - ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it is fixed in r1p1. @@ -946,7 +958,7 @@ GIC Errata Workarounds -------------- -*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.* .. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 .. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h index 4a3ac775e..542907877 100644 --- a/include/lib/cpus/aarch64/cortex_x3.h +++ b/include/lib/cpus/aarch64/cortex_x3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,6 +25,11 @@ #define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4) #define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7) +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR_EL1 S3_0_C15_C1_0 + /******************************************************************************* * CPU Auxiliary Control register 2 specific definitions. ******************************************************************************/ diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index 2e6e8b6a9..0dc34f7ac 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -72,6 +72,19 @@ workaround_reset_end cortex_a78c, ERRATUM(2395411) check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) +workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027 + ldr x0, =0x3 + msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 + ldr x0, =0xEE010F10 + msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 + ldr x0, =0xFF1F0FFE + msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 + ldr x0, =0x100000004003FF + msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 +workaround_reset_end cortex_a78c, ERRATUM(2683027) + +check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2) + workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55) diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 7e9a7fcf6..ea8926796 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,6 +33,18 @@ workaround_reset_end cortex_x3, ERRATUM(2070301) check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) +workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 + sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) +workaround_reset_end cortex_x3, ERRATUM(2266875) + +check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0) + +workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 + sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) +workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB + +check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1) + workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 0ad5e7819..a99c08295 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -388,6 +388,10 @@ CPU_FLAG_LIST += ERRATA_A78C_2376749 # to revisions r0p1 and r0p2 of the A78C cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78C_2395411 +# Flag to apply erratum 2683027 workaround during reset. This erratum applies +# to revisions r0p1 and r0p2 of the A78C cpu. It is still open. +CPU_FLAG_LIST += ERRATA_A78C_2683027 + # Flag to apply erratum 2712575 workaround for non-arm interconnect ip. This # erratum applies to revisions r0p1 and r0p2 of the A78C cpu. # It is still open. @@ -774,6 +778,14 @@ CPU_FLAG_LIST += ERRATA_X2_2778471 # still open. CPU_FLAG_LIST += ERRATA_X3_2070301 +# Flag to apply erratum 2266875 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1. +CPU_FLAG_LIST += ERRATA_X3_2266875 + +# Flag to apply erratum 2302506 workaround during reset. This erratum applies +# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2. +CPU_FLAG_LIST += ERRATA_X3_2302506 + # Flag to apply erratum 2313909 workaround on powerdown. This erratum applies # to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1. CPU_FLAG_LIST += ERRATA_X3_2313909 diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c index 537cb5cfc..f1342ad13 100644 --- a/services/std_svc/errata_abi/errata_abi_main.c +++ b/services/std_svc/errata_abi/errata_abi_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -237,12 +237,13 @@ struct em_cpu_list cpu_list[] = { [3] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638}, [4] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749}, [5] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411}, - [6] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \ + [6] = {2683027, 0x01, 0x02, ERRATA_A78C_2683027}, + [7] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \ ERRATA_NON_ARM_INTERCONNECT}, - [7] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232}, - [8] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121}, - [9] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484}, - [10 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [8] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232}, + [9] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121}, + [10] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484}, + [11 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_A78C_H_INC */ @@ -446,12 +447,14 @@ struct em_cpu_list cpu_list[] = { .cpu_partnumber = CORTEX_X3_MIDR, .cpu_errata_list = { [0] = {2070301, 0x00, 0x12, ERRATA_X3_2070301}, - [1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909}, - [2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, - [3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, - [4] = {2743088, 0x00, 0x11, ERRATA_X3_2743088}, - [5] = {2779509, 0x00, 0x11, ERRATA_X3_2779509}, - [6 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [1] = {2266875, 0x00, 0x10, ERRATA_X3_2266875}, + [2] = {2302506, 0x00, 0x11, ERRATA_X3_2302506}, + [3] = {2313909, 0x00, 0x10, ERRATA_X3_2313909}, + [4] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, + [5] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, + [6] = {2743088, 0x00, 0x11, ERRATA_X3_2743088}, + [7] = {2779509, 0x00, 0x11, ERRATA_X3_2779509}, + [8 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_X3_H_INC */