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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge "fix(smccc): ensure that mpidr passed through SMC is valid" into integration
This commit is contained in:
commit
e0c7d8f56c
9 changed files with 46 additions and 45 deletions
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@ -80,6 +80,20 @@ unsigned int plat_my_core_pos(void);
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int plat_core_pos_by_mpidr(u_register_t mpidr);
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int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
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/*******************************************************************************
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* Simple routine to determine whether a mpidr is valid or not.
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******************************************************************************/
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static inline bool is_valid_mpidr(u_register_t mpidr)
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{
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int pos = plat_core_pos_by_mpidr(mpidr);
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if ((pos < 0) || ((unsigned int)pos >= PLATFORM_CORE_COUNT)) {
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return false;
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}
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return true;
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}
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#if STACK_PROTECTOR_ENABLED
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/*
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* Return a new value to be used for the stack protection's canary.
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@ -165,7 +165,7 @@ int pmf_get_timestamp_smc(unsigned int tid,
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/* Search for registered service. */
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svc_desc = get_service(tid);
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if ((svc_desc == NULL) || (plat_core_pos_by_mpidr(mpidr) < 0)) {
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if (svc_desc == NULL) {
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*ts_value = 0;
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return -EINVAL;
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} else {
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@ -26,6 +26,10 @@ uintptr_t pmf_smc_handler(unsigned int smc_fid,
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int rc;
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unsigned long long ts_value;
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/* Determine if the cpu exists of not */
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if (!is_valid_mpidr(x2))
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return PSCI_E_INVALID_PARAMS;
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if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
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x1 = (uint32_t)x1;
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@ -817,20 +817,6 @@ void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
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}
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}
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/*******************************************************************************
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* Simple routine to determine whether a mpidr is valid or not.
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******************************************************************************/
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int psci_validate_mpidr(u_register_t mpidr)
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{
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int pos = plat_core_pos_by_mpidr(mpidr);
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if ((pos < 0) || ((unsigned int)pos >= PLATFORM_CORE_COUNT)) {
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return PSCI_E_INVALID_PARAMS;
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* This function determines the full entrypoint information for the requested
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* PSCI entrypoint on power on/resume and returns it.
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@ -29,9 +29,8 @@ int psci_cpu_on(u_register_t target_cpu,
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int rc;
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entry_point_info_t ep;
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/* Determine if the cpu exists of not */
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rc = psci_validate_mpidr(target_cpu);
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if (rc != PSCI_E_SUCCESS)
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/* Validate the target CPU */
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if (!is_valid_mpidr(target_cpu))
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return PSCI_E_INVALID_PARAMS;
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/* Validate the entry point and get the entry_point_info */
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@ -245,19 +244,18 @@ int psci_cpu_off(void)
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int psci_affinity_info(u_register_t target_affinity,
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unsigned int lowest_affinity_level)
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{
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int ret;
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unsigned int target_idx;
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/* Validate the target affinity */
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if (!is_valid_mpidr(target_affinity))
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return PSCI_E_INVALID_PARAMS;
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/* We dont support level higher than PSCI_CPU_PWR_LVL */
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if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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/* Calculate the cpu index of the target */
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ret = plat_core_pos_by_mpidr(target_affinity);
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if (ret == -1) {
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return PSCI_E_INVALID_PARAMS;
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}
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target_idx = (unsigned int)ret;
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target_idx = (unsigned int) plat_core_pos_by_mpidr(target_affinity);
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/*
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* Generic management:
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@ -285,6 +283,10 @@ int psci_migrate(u_register_t target_cpu)
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int rc;
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u_register_t resident_cpu_mpidr;
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/* Validate the target cpu */
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if (!is_valid_mpidr(target_cpu))
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return PSCI_E_INVALID_PARAMS;
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rc = psci_spd_migrate_info(&resident_cpu_mpidr);
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if (rc != PSCI_TOS_UP_MIG_CAP)
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return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
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@ -298,8 +300,7 @@ int psci_migrate(u_register_t target_cpu)
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return PSCI_E_NOT_PRESENT;
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/* Check the validity of the specified target cpu */
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rc = psci_validate_mpidr(target_cpu);
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if (rc != PSCI_E_SUCCESS)
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if (!is_valid_mpidr(target_cpu))
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return PSCI_E_INVALID_PARAMS;
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assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL));
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@ -339,8 +340,7 @@ int psci_node_hw_state(u_register_t target_cpu,
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int rc;
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/* Validate target_cpu */
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rc = psci_validate_mpidr(target_cpu);
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if (rc != PSCI_E_SUCCESS)
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if (!is_valid_mpidr(target_cpu))
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return PSCI_E_INVALID_PARAMS;
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/* Validate power_level against PLAT_MAX_PWR_LVL */
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@ -61,15 +61,7 @@ int psci_cpu_on_start(u_register_t target_cpu,
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{
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int rc;
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aff_info_state_t target_aff_state;
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int ret = plat_core_pos_by_mpidr(target_cpu);
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unsigned int target_idx;
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/* Calling function must supply valid input arguments */
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assert(ret >= 0);
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assert((unsigned int)ret < PLATFORM_CORE_COUNT);
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assert(ep != NULL);
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target_idx = (unsigned int)ret;
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unsigned int target_idx = (unsigned int)plat_core_pos_by_mpidr(target_cpu);
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/*
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* This function must only be called on platforms where the
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@ -286,7 +286,6 @@ extern const spd_pm_ops_t *psci_spd_pm;
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int psci_validate_power_state(unsigned int power_state,
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psci_power_state_t *state_info);
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void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info);
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int psci_validate_mpidr(u_register_t mpidr);
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void psci_init_req_local_pwr_states(void);
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#if PSCI_OS_INIT_MODE
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void psci_update_req_local_pwr_states(unsigned int end_pwrlvl,
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@ -181,10 +181,8 @@ static int psci_get_stat(u_register_t target_cpu, unsigned int power_state,
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psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
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plat_local_state_t local_state;
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/* Validate the target_cpu parameter and determine the cpu index */
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/* Determine the cpu index */
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target_idx = (unsigned int) plat_core_pos_by_mpidr(target_cpu);
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if (target_idx == (unsigned int) -1)
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return PSCI_E_INVALID_PARAMS;
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/* Validate the power_state parameter */
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if (psci_plat_pm_ops->translate_power_state_by_mpidr == NULL)
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@ -228,6 +226,11 @@ u_register_t psci_stat_residency(u_register_t target_cpu,
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unsigned int power_state)
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{
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psci_stat_t psci_stat;
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/* Validate the target cpu */
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if (!is_valid_mpidr(target_cpu))
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return 0;
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int rc = psci_get_stat(target_cpu, power_state, &psci_stat);
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if (rc == PSCI_E_SUCCESS)
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@ -241,6 +244,11 @@ u_register_t psci_stat_count(u_register_t target_cpu,
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unsigned int power_state)
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{
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psci_stat_t psci_stat;
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/* Validate the target cpu */
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if (!is_valid_mpidr(target_cpu))
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return 0;
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int rc = psci_get_stat(target_cpu, power_state, &psci_stat);
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if (rc == PSCI_E_SUCCESS)
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@ -35,8 +35,6 @@
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#define LOWEST_INTR_PRIORITY 0xff
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#define is_valid_affinity(_mpidr) (plat_core_pos_by_mpidr(_mpidr) >= 0)
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CASSERT(PLAT_SDEI_CRITICAL_PRI < PLAT_SDEI_NORMAL_PRI,
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sdei_critical_must_have_higher_priority);
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@ -262,7 +260,7 @@ static int validate_flags(uint64_t flags, uint64_t mpidr)
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/* Validate flags */
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switch (flags) {
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case SDEI_REGF_RM_PE:
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if (!is_valid_affinity(mpidr))
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if (!is_valid_mpidr(mpidr))
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return SDEI_EINVAL;
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break;
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case SDEI_REGF_RM_ANY:
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@ -926,7 +924,7 @@ static int sdei_signal(int ev_num, uint64_t target_pe)
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return SDEI_EINVAL;
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/* Validate target */
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if (plat_core_pos_by_mpidr(target_pe) < 0)
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if (!is_valid_mpidr(target_pe))
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return SDEI_EINVAL;
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/* Raise SGI. Platform will validate target_pe */
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