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fix(cpus): workaround for Cortex-A715 erratum 2561034

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Cortex-A715 erratum 2561034 is a Cat B erratum that applies to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit[26] in CPUACTLR2_EL1. Setting this
bit is not expected to have a significant performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: I377f250a2994b6ced3ac7d93f947af6ceb690d49
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
This commit is contained in:
Bipin Ravi 2024-01-25 16:18:20 -06:00 • committed by Sona Mathew
parent 17bef2248d
commit 6a6b282378
5 changed files with 24 additions and 4 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -872,6 +872,10 @@ For Cortex-A520, the following errata build flags are defined :
For Cortex-A715, the following errata build flags are defined :
- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to
Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
It is fixed in r1p1.
- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715
CPU and affects system configurations that do not use an ARM interconnect
IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed

7
include/lib/cpus/aarch64/cortex_a715.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,6 +12,11 @@
/* Cortex-A715 loop count for CVE-2022-23960 mitigation */
#define CORTEX_A715_BHB_LOOP_COUNT U(38)
/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.
******************************************************************************/
#define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/

8
lib/cpus/aarch64/cortex_a715.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -26,6 +26,12 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
#endif /* WORKAROUND_CVE_2022_23960 */
workaround_runtime_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034
sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26)
workaround_runtime_end cortex_a715, ERRATUM(2561034), NO_ISB
check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0)
workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*

4
lib/cpus/cpu-ops.mk
View file

@ -903,6 +903,10 @@ CPU_FLAG_LIST += ERRATA_V2_2779510
# This erratum applies to revisions r0p0, r0p1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2801372
# Flag to apply erratum 2561034 workaround during reset. This erratum applies
# only to revision r1p0. It is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_A715_2561034
# Flag to apply erratum 2701951 workaround for non-arm interconnect ip.
# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_A715_2701951

5
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -435,9 +435,10 @@ struct em_cpu_list cpu_list[] = {
{
.cpu_partnumber = CORTEX_A715_MIDR,
.cpu_errata_list = {
[0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
[0] = {2561034, 0x10, 0x10, ERRATA_A715_2561034},
[1] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
ERRATA_NON_ARM_INTERCONNECT},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A715_H_INC */