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6a6b282378
Cortex-A715 erratum 2561034 is a Cat B erratum that applies to revision r1p0 and is fixed in r1p1. The workaround is to set bit[26] in CPUACTLR2_EL1. Setting this bit is not expected to have a significant performance impact. SDEN documentation: https://developer.arm.com/documentation/SDEN2148827/latest Change-Id: I377f250a2994b6ced3ac7d93f947af6ceb690d49 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
91 lines
2.8 KiB
ArmAsm
91 lines
2.8 KiB
ArmAsm
/*
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a715.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_runtime_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034
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sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26)
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workaround_runtime_end cortex_a715, ERRATUM(2561034), NO_ISB
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check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0)
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workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A715 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_a715
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a715, CVE(2022, 23960)
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check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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cpu_reset_func_start cortex_a715
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_a715
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a715_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_A715_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A715_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a715_core_pwr_dwn
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errata_report_shim cortex_a715
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/* ---------------------------------------------
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* This function provides Cortex-A715 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a715_regs, "aS"
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cortex_a715_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a715_cpu_reg_dump
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adr x6, cortex_a715_regs
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mrs x8, CORTEX_A715_CPUECTLR_EL1
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ret
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endfunc cortex_a715_cpu_reg_dump
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declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \
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cortex_a715_reset_func, \
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cortex_a715_core_pwr_dwn
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