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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge "feat(fvp): delegate FFH RAS handling to SP" into integration
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
17bef2248d
3 changed files with 149 additions and 8 deletions
121
plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c
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121
plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c
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@ -0,0 +1,121 @@
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <inttypes.h>
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#include <stdint.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/extensions/ras.h>
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#include <plat/common/platform.h>
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#include <services/el3_spmd_logical_sp.h>
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#include <services/ffa_svc.h>
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#include <services/sdei.h>
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#define CACTUS_SP_RAS_DELEGATE_CMD 0x72617365
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#define EVENT_NOTIFY_OS_RAS_ERROR U(5000)
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/*
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* Note: Typical RAS error handling flow with Firmware First Handling
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*
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* Step 1: Exception resulting from a RAS error in the normal world is routed to
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* EL3.
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* Step 2: This exception is typically signaled as either a synchronous external
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* abort or SError or interrupt. TF-A (EL3 firmware) delegates the
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* control to platform specific handler built on top of the RAS helper
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* utilities.
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* Step 3: With the help of a Logical Secure Partition, TF-A sends a direct
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* message to dedicated S-EL0 (or S-EL1) RAS Partition managed by SPMC.
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* TF-A also populates a shared buffer with a data structure containing
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* enough information (such as system registers) to identify and triage
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* the RAS error.
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* Step 4: RAS SP generates the Common Platform Error Record (CPER) and shares
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* it with normal world firmware and/or OS kernel through a reserved
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* buffer memory.
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* Step 5: RAS SP responds to the direct message with information necessary for
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* TF-A to notify the OS kernel.
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* Step 6: Consequently, TF-A dispatches an SDEI event to notify the OS kernel
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* about the CPER records for further logging.
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*/
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static int injected_fault_handler(const struct err_record_info *info,
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int probe_data, const struct err_handler_data *const data)
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{
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/*
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* At the moment, an FF-A compatible SP that supports RAS firmware is
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* not available. Hence the sequence below does not exactly follow the
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* steps outlined above. Therefore, some steps are essentially spoofed.
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* The handling of RAS error is completely done in EL3 firmware.
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*/
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uint64_t status, cactus_cmd_ret;
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int ret, event_num;
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cpu_context_t *ns_cpu_context;
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/* Get a reference to the non-secure context */
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ns_cpu_context = cm_get_context(NON_SECURE);
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assert(ns_cpu_context != NULL);
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/*
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* The faulting error record is already selected by the SER probe
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* function.
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*/
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status = read_erxstatus_el1();
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ERROR("Fault reported by system error record %d on 0x%lx: status=0x%" PRIx64 "\n",
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probe_data, read_mpidr_el1(), status);
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ERROR(" exception reason=%u syndrome=0x%" PRIx64 "\n", data->ea_reason,
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data->flags);
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/* Clear error */
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write_erxstatus_el1(status);
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/*
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* Initiate an EL3 direct message from LSP to Cactus RAS Secure
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* Partition (ID 8001). Currently, the payload is being spoofed.
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* The direct message response contains the SDEI event ID for the
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* associated RAS error.
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*/
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(void)plat_spmd_logical_sp_smc_handler(0, 0, 0, CACTUS_SP_RAS_DELEGATE_CMD,
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EVENT_NOTIFY_OS_RAS_ERROR,
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NULL, ns_cpu_context, 0);
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cactus_cmd_ret = read_ctx_reg(get_gpregs_ctx(ns_cpu_context), CTX_GPREG_X3);
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event_num = (int)read_ctx_reg(get_gpregs_ctx(ns_cpu_context), CTX_GPREG_X4);
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if (cactus_cmd_ret != 0) {
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ERROR("RAS error could not be handled by SP: %lx\n", cactus_cmd_ret);
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panic();
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}
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if (event_num != EVENT_NOTIFY_OS_RAS_ERROR) {
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ERROR("Unexpected event id sent by RAS SP: %d\n", event_num);
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panic();
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}
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/* Dispatch the event to the SDEI client */
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ret = sdei_dispatch_event(event_num);
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if (ret < 0) {
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ERROR("Can't dispatch event to SDEI\n");
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panic();
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} else {
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INFO("SDEI event dispatched\n");
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}
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return 0;
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}
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struct ras_interrupt fvp_ras_interrupts[] = {
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};
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struct err_record_info fvp_err_records[] = {
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/* Record for injected fault */
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ERR_RECORD_SYSREG_V1(0, 2, ras_err_ser_probe_sysreg,
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injected_fault_handler, NULL),
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};
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REGISTER_ERR_RECORD_INFO(fvp_err_records);
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REGISTER_RAS_INTERRUPTS(fvp_ras_interrupts);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -416,7 +416,7 @@ defined(IMAGE_BL2) && MEASURED_BOOT
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#define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT
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#define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT
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#else
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#if PLATFORM_TEST_RAS_FFH
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#if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP
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#define PLAT_ARM_PRIVATE_SDEI_EVENTS \
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ARM_SDEI_PRIVATE_EVENTS, \
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SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -399,11 +399,15 @@ endif
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endif
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ifeq (${HANDLE_EA_EL3_FIRST_NS},1)
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ifeq (${ENABLE_FEAT_RAS},1)
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BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c
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else
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BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
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endif
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ifeq (${ENABLE_FEAT_RAS},1)
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ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1)
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BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c
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else
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BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c
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endif
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else
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BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
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endif
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endif
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ifneq (${ENABLE_STACK_PROTECTOR},0)
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@ -518,6 +522,22 @@ ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
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endif
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endif
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$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP))
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ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1)
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ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
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$(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP")
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endif
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ifeq (${ENABLE_SPMD_LP}, 0)
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$(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1")
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endif
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ifeq (${ENABLE_FEAT_RAS}, 0)
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$(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1")
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endif
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ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
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$(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1")
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endif
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endif
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ifeq (${ERRATA_ABI_SUPPORT}, 1)
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include plat/arm/board/fvp/fvp_cpu_errata.mk
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endif
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