Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 01:24:27 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(cpus): workaround for Neoverse V2 erratum 2662553

Browse source 
Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size statically to it's full size.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I3bc43e7299c17db8a6771a547515ffb2a172fa0f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
This commit is contained in:
Bipin Ravi 2023-10-17 18:35:55 -05:00
parent ccd8c0230c
commit 912c4090ff
5 changed files with 25 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
docs/design/cpu-specific-build-macros.rst
View file

@ -528,6 +528,10 @@ For Neoverse V2, the following errata build flags are defined :
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still
open.
- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
r0p2.
- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2
CPU, this affects system configurations that do not use and ARM interconnect
IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed

3
include/lib/cpus/aarch64/neoverse_v2.h
View file

@ -30,6 +30,9 @@
#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11)
#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0)
#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB U(0)
#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH U(3)
/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.

7
lib/cpus/aarch64/neoverse_v2.S
View file

@ -29,6 +29,13 @@ workaround_reset_end neoverse_v2, ERRATUM(2331132)
check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2)
workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553
sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \
NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH
workaround_reset_end neoverse_v2, ERRATUM(2662553)
check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1)
workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105
sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0
workaround_reset_end neoverse_v2, ERRATUM(2719105)

4
lib/cpus/cpu-ops.mk
View file

@ -826,6 +826,10 @@ CPU_FLAG_LIST += ERRATA_A510_2684597
# to revisions r0p0, r0p1 and r0p2. It is still open.
CPU_FLAG_LIST += ERRATA_V2_2331132
# Flag to apply erratum 2662553 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2662553
# Flag to apply erratum 2719103 workaround for non-arm interconnect ip. This
# erratum applies to revisions r0p0, rop1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2719103

13
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -413,13 +413,14 @@ struct em_cpu_list cpu_list[] = {
.cpu_partnumber = NEOVERSE_V2_MIDR,
.cpu_errata_list = {
[0] = {2331132, 0x00, 0x02, ERRATA_V2_2331132},
[1] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
[1] = {2662553, 0x00, 0x01, ERRATA_V2_2662553},
[2] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
ERRATA_NON_ARM_INTERCONNECT},
[2] = {2719105, 0x00, 0x01, ERRATA_V2_2719105},
[3] = {2743011, 0x00, 0x01, ERRATA_V2_2743011},
[4] = {2779510, 0x00, 0x01, ERRATA_V2_2779510},
[5] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
[6 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[3] = {2719105, 0x00, 0x01, ERRATA_V2_2719105},
[4] = {2743011, 0x00, 0x01, ERRATA_V2_2743011},
[5] = {2779510, 0x00, 0x01, ERRATA_V2_2779510},
[6] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
[7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_V2_H_INC */