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912c4090ff
Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The workaround is to set L2 TQ size statically to it's full size. SDEN documentation: https://developer.arm.com/documentation/SDEN-2332927/latest Change-Id: I3bc43e7299c17db8a6771a547515ffb2a172fa0f Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
56 lines
2.5 KiB
C
56 lines
2.5 KiB
C
/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_V2_H
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#define NEOVERSE_V2_H
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#define NEOVERSE_V2_MIDR U(0x410FD4F0)
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/* Neoverse V2 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_V2_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Extended Control register 2 specific definitions.
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******************************************************************************/
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#define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
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#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11)
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#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0)
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#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB U(0)
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#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH U(3)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
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/*******************************************************************************
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* CPU Auxiliary Control register 3 specific definitions.
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******************************************************************************/
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#define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2
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#define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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#define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
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#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
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#endif /* NEOVERSE_V2_H */
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