Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 01:24:27 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(cpus): workaround for Cortex-A520 erratum 2858100

Browse source 
Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUACTLR_EL1.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5a07163f919352583b03328abd5659bf7b268677
This commit is contained in:
Arvind Ram Prakash 2023-12-08 20:19:58 -06:00
parent ae19093f2a
commit 34db3531ba
5 changed files with 18 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
docs/design/cpu-specific-build-macros.rst
View file

@ -846,6 +846,10 @@ For Cortex-A520, the following errata build flags are defined :
Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the
CPU and is still open.
- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to
Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1.
It is still open.
For Cortex-A715, the following errata build flags are defined :
- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715

2
include/lib/cpus/aarch64/cortex_a520.h
View file

@ -12,6 +12,8 @@
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************

6
lib/cpus/aarch64/cortex_a520.S
View file

@ -26,6 +26,12 @@ workaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792
workaround_reset_end cortex_a520, ERRATUM(2630792)
check_erratum_ls cortex_a520, ERRATUM(2630792), CPU_REV(0, 1)
workaround_reset_start cortex_a520, ERRATUM(2858100), ERRATA_A520_2858100
sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(29)
workaround_reset_end cortex_a520, ERRATUM(2858100)
check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1)
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------

4
lib/cpus/cpu-ops.mk
View file

@ -847,6 +847,10 @@ CPU_FLAG_LIST += ERRATA_A510_2684597
# to revisions r0p0, r0p1 of the Cortex-A520 cpu and is still open.
CPU_FLAG_LIST += ERRATA_A520_2630792
# Flag to apply erratum 2858100 workaround during reset. This erratum
# applies to revision r0p0 and r0p1 of the Cortex-A520 cpu and is still open.
CPU_FLAG_LIST += ERRATA_A520_2858100
# Flag to apply erratum 2331132 workaround during reset. This erratum applies
# to revisions r0p0, r0p1 and r0p2. It is still open.
CPU_FLAG_LIST += ERRATA_V2_2331132

3
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -460,7 +460,8 @@ struct em_cpu_list cpu_list[] = {
.cpu_partnumber = CORTEX_A520_MIDR,
.cpu_errata_list = {
[0] = {2630792, 0x00, 0x01, ERRATA_A520_2630792},
[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[1] = {2858100, 0x00, 0x01, ERRATA_A520_2858100},
[2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A520_H_INC */