diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index b29c7525c..ce4507603 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -846,6 +846,10 @@ For Cortex-A520, the following errata build flags are defined :
    Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the
    CPU and is still open.
 
+-  ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to
+   Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1.
+   It is still open.
+
 For Cortex-A715, the following errata build flags are defined :
 
 -  ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715
diff --git a/include/lib/cpus/aarch64/cortex_a520.h b/include/lib/cpus/aarch64/cortex_a520.h
index 1c5f8862c..619a15d1c 100644
--- a/include/lib/cpus/aarch64/cortex_a520.h
+++ b/include/lib/cpus/aarch64/cortex_a520.h
@@ -12,6 +12,8 @@
 /*******************************************************************************
  * CPU Extended Control register specific definitions
  ******************************************************************************/
+#define CORTEX_A520_CPUACTLR_EL1				S3_0_C15_C1_0
+
 #define CORTEX_A520_CPUECTLR_EL1				S3_0_C15_C1_4
 
 /*******************************************************************************
diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S
index 92f13f469..74ecbf7c9 100644
--- a/lib/cpus/aarch64/cortex_a520.S
+++ b/lib/cpus/aarch64/cortex_a520.S
@@ -26,6 +26,12 @@ workaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792
 workaround_reset_end cortex_a520, ERRATUM(2630792)
 
 check_erratum_ls cortex_a520, ERRATUM(2630792), CPU_REV(0, 1)
+
+workaround_reset_start cortex_a520, ERRATUM(2858100), ERRATA_A520_2858100
+	sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(29)
+workaround_reset_end cortex_a520, ERRATUM(2858100)
+
+check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1)
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 68d6ef836..302f697c8 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -847,6 +847,10 @@ CPU_FLAG_LIST += ERRATA_A510_2684597
 # to revisions r0p0, r0p1 of the Cortex-A520 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_A520_2630792
 
+# Flag to apply erratum 2858100 workaround during reset. This erratum
+# applies to revision r0p0 and r0p1 of the Cortex-A520 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_A520_2858100
+
 # Flag to apply erratum 2331132 workaround during reset. This erratum applies
 # to revisions r0p0, r0p1 and r0p2. It is still open.
 CPU_FLAG_LIST += ERRATA_V2_2331132
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 724d363e6..8f1f1fe80 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -460,7 +460,8 @@ struct em_cpu_list cpu_list[] = {
 	.cpu_partnumber = CORTEX_A520_MIDR,
 	.cpu_errata_list = {
 		[0] = {2630792, 0x00, 0x01, ERRATA_A520_2630792},
-		[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+		[1] = {2858100, 0x00, 0x01, ERRATA_A520_2858100},
+		[2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
 #endif /* CORTEX_A520_H_INC */