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Cortex-A520 erratum 2858100 is a Cat B erratum that applies to all revisions <=r0p1 and is still open. The workaround is to set bit[29] of CPUACTLR_EL1. SDEN Documentation: https://developer.arm.com/documentation/SDEN-2444153/latest Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I5a07163f919352583b03328abd5659bf7b268677
30 lines
1.1 KiB
C
30 lines
1.1 KiB
C
/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A520_H
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#define CORTEX_A520_H
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#define CORTEX_A520_MIDR U(0x410FD800)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Auxiliary Control register 1 specific definitions.
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******************************************************************************/
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#define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A520_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* CORTEX_A520_H */
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