* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'
When BL2 is enabled as the entrypoint in the reset vector, none of the
TL initialisation ordinarily performed in BL1 will have been done. This
change ensures that BL2 has a secure TL to pass information onto BL31
through.
Change-Id: I553b0b7aac9390cd6a2d63471b81ddc72cc40a60
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Leverage the framework between BL1 and BL2. Migrate all handoff
structures to the TL.
Change-Id: I79ff3a319596b5656184cde10b5204b10a4d03bb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
`TL_TAG_RW_MEM_LAYOUT64` encapsulates a structure used to represent the
layout of a region of memory on 64-bit platforms [2]. In TF-A this is
used to represent the `meminfo_t` structure passed between BL1 and BL2,
which provides BL2 with information about the space it has available in
BL2. The `TL_TAG_TB_FW_CONFIG` entry type encapsulates the trusted
bootloader firmware configuration [1].
[1] https://github.com/FirmwareHandoff/firmware_handoff/pull/37
[2] https://github.com/FirmwareHandoff/firmware_handoff/pull/36
Change-Id: I1e0eeec2ec204e469896490d42a9dce9b1b2f209
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Layout calculation is spread out between core BL1 logic and common
platform code. Relocate these into common platform code so they are
organised logically.
Change-Id: I8b05403e41b800957a0367316cecd373d10bb1a4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent models. Load the HW_CONFIG as a TE along with entry point
parameters for BL31 execution.
Change-Id: I7c4c6e8353ca978a13520fb3e15fb2803f0f1d0e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
* changes:
feat(docs): update maintainer list for neoverse_rd
refactor(neoverse-rd): remove soc_css.mk from common makefile
refactor(neoverse-rd): unify GIC SPI range macros
refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file
feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms
feat(rdn2): enable AMU if present on the platform
feat(rdn2): enable MTE2 if present on the platform
refactor(neoverse-rd): move defines out of platform_def.h
refactor(neoverse-rd): add defines for ROM, SRAM and DRAM2
refactor(neoverse-rd): define naming convention for RoS macros
refactor(neoverse-rd): define naming convention for CSS macros
refactor(neoverse-rd): refactor mmap macro for RoS device memory region
refactor(neoverse-rd): refactor mmap macro for CSS device memory region
refactor(neoverse-rd): set mmap naming convention
refactor(neoverse-rd): rename nrd_plat_v2.c to align with convention
refactor(neoverse-rd): refactor nrd_soc_css_def_v2.h file
refactor(neoverse-rd): refactor nrd_soc_platform_def_v2.h file
refactor(neoverse-rd): refactor nrd_base_platform_def.h
refactor(neoverse-rd): header files for second generation platforms
Add Rohit.Mathew@arm.com to the maintainer list for Neoverse Reference
Design platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1b8a5714e2707162dd973d9a50215d0a6b622eb1
The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 within the
SOC specification. However, as none of the Neoverse reference design
platforms necessitate the initialization of PCIe or NIC400, remove the
soc_css.mk from the common makefile.
Additionally, empty initialization functions for PCIe and NIC400 are
added to satisfy the requirements of the plat/arm common code, which
expects these functions to be present.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935
The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish the convention "NRD_CHIP<x>_SPI_MIN" and
"NRD_CHIP<x>_SPI_MAX" for use across all Neoverse Reference Design
multichip platforms.
Furthermore, extend this naming convention to RD-N2-Cfg2 and introduce
similar macros.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idca2a8c66579f05e712e3b6e95204fedc122cf23
Consolidate and organize platform port definitions within the
nrd_plat_arm_def2.h file. Remove direct references to addresses with
corresponding RoS or CSS definitions.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic43cff90d2cf45760b3f808732754cf7c05a814a
SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value to 0.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib503c5552e2b8fee928b2392ba40805664d857d7
Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could access system registers relevant to AMU without causing a trap to
EL3.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic9aa435af54eddacdaa49e69f25893ddaa977e3e
MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
could potentially access the featre registers leading EL3 traps.
Therefore, set MTE2 build option to '2' to enable the feature only if
its implemented on the platform.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I97c341ac38485937eb18ce9bdcffec26c0e5e76d
As RD-N1-Edge is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.
Change-Id: I6af06e7bd162747aab72384185951d218b388ed3
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Presently, the second generation platforms have direct references to CSS
and ROS specific addresses within RD-N2's platform header file
(platform_def.h). Moreover, there are platform port specific macros
defined within platform_def.h To enhance organization and
appropriateness, relocate these definitions to nrd_css_def2.h,
nrd_ros_def2.h and nrd_arm_platform_def1.h files accordingly. Reuse
these definitions within the platform_def.h files as needed.
Additionally, remove reference to the unused PLAT_ARM_GICC_BASE macro
from the individual platform_def.h file.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9a237c3ae28d7e209188e2c37c8494b4a420ee83
As SGI-575 is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.
Change-Id: Ic9171a3e1bec198d9305e75ac5cae4b40498537e
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
In the current setup, the base and size of the ROM, SRAM, and DRAM2
regions are directly defined in the nrd_fw_def2.h file for N2 CPU based
platforms. To enhance modularity and appropriateness, introduce macros
for these definitions in the respective css file (nrd_css_def2.h). While
the maximum sizes for ROM, SRAM, and DRAM2 are specified in the css
specification, the actual implementation sizes may vary. Consequently,
relocate the size macros to the platform-specific platform_def.h file
for individual platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I30988bf63cf942f68188a70697cc43cb6af96a9c
As part of the refactoring for the second generation platforms,
introduce a naming convention for macros within nrd_ros_def2.h and
nrd_ros_fw_def2.h. All macros, except those related to page table
entries, must adhere to the format NRD_ROS_<name>. Page table entry
macros are handled separately and are not part of this patch.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ifcdc30b1c80b9848b793de2013095fc98d57bec6
As part of the refactoring for the second generation of platforms,
introduce a naming convention for macros within nrd_css_def2.h and
nrd_css_fw_def2.h. All macros, except those related to page table
entries, must adhere to the format NRD_CSS_<name>. Page table entry
macros are handled separately and are not part of this patch.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib168320e12f06cd034342c011909896de463ab27
There are two macros that define ROS device memory map range and
attributes - one for local chip and the other for remote chip. Refactor
these two macros into a single macro that uses the chip ID to identify
the local or the remote chip.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I58eb65c2f046b6074f848f1448cd10a7dcc37f74
There are two macros that define CSS device memory map range and
attributes - one for local chip and the other for remote chip. Refactor
these two macros into a single macro that uses the chip ID to identify
the local or the remote chip. While at it, rename the macro that defines
the memory map range and attributes for the remote shared RAM region.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ieddd5c81f6261490dbacb97160858903e56d327a
Presently, for the second generation platforms based on the N2 CPU,
macros related to page table entries lack a consistent naming
convention. This absence may lead to potential mix-ups, such as css
definitions in soc files, and can contribute to decreased code clarity.
To address this, establish the following naming convention:
- NRD_CSS_<name>_MMAP for CSS related page table entries
- NRD_ROS_<name>_MMAP for ROS related page table entries
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I7bf1f9b0ddfd0444c802a23143de6a163f127731
Header files for N2 CPU based platforms currently use "2" as
a suffix. Rename the common source file, nrd_plat_v2.c used by these
platforms to nrd_plat2.c to align with this convention.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I36b138a0a4dff8087e52f0f2cbc21abc03a793ad
Continuing the refactoring of the various definition for platforms based
on N2/V2 CPU, refactor the definitions in the nrd_soc_css_def_v2.h file
into the following files as appropriate.
- nrd_ros_def2.h: includes RoS hardware related definitions
- nrd_plat_arm_def2.h: includes platform port related definitions
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib447e67a0a42722735297b27b7f5017bc146156c
Continuing the refactoring of the various definitions for the second
generation platforms based on the N2/V2 CPU, refactor the definitions in
the nrd_soc_platform_def_v2.h file into the following files as
appropriate.
- nrd_ros_def2.h: includes RoS hardware related definitions
- nrd_ros_fw_def2.h: includes RoS firmware related definitions
- nrd_plat_arm_def2.h: includes platform port related definitions
RoS (Rest Of System) is used to refer to the part of the reference
design platform that excludes CSS. The file inclusions in the
platform_def.h file of the platforms have been updated accordingly.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I393e6f4a84be45f1781ea281bd55fa813803f6db
The nrd_base_platform_def.h file includes CSS, RoS, firmware and
platform port related definitions. This approach of consolidating the
various definitions for multiple generation of platforms into the
nrd_base_platform_def.h file is not scaling well.
So in preparation of moving away from the use of nrd_base_platform_def.h
file for the second generation platforms based on N2/V2 CPUs, split the
definitions in this file into multiple include files. The new files into
which the definitions are refactored are -
- nrd_css_def2.h: includes CSS hardware related definitions
- nrd_css_fw_def2.h: includes CSS firmware related definitions
- nrd_ros_fw_def2.h: includes RoS firmware related definitions
- nrd_plat_arm_def2.h: includes platform port elated definitions
RoS (Rest Of System) is used to refer to the part of the reference
design platform that excludes CSS. The definitions that are only
relavant to the aforementioned platforms have been refactored from the
nrd_base_platform_def.h file.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I45f680857328fa77f0977897490b225bdb29efe4
Presently, platforms such as RD-N2, RD-N2-Cfg1, RD-N2-Cfg2 and RD-V2
utilize nrd_soc_platform_def_v2.h and nrd_soc_css_def_v2.h for all css
and soc-related defines. So move these two header files into a new
directory named 'nrd2'. This new directory will serve as the container
of header files that are specific to the former stated platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I51ba0944dea91ae81e1840947d2e9af9b28d561d
The title for RD-N1-Edge was written as "RD-N1 Edge" in the changelog
file. This has been corrected to "RD-N1-Edge" to pedantically reflect
the proper name for the platform.
Change-Id: I17a0f8745117674482e7c668109d821c81e35d1d
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As RD-V1-MC would need a dedicated scope for use, define the scope
'rdv1mc' under the subsection within Neoverse-RD platforms.
Change-Id: I5fd53ce89815e355b595fe7ff066386842b7af03
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As RD-V1 would need a dedicated scope for use, define the scope
'rdv1' under the subsection within Neoverse-RD platforms.
Change-Id: I035499e1ce85d6efd54ac4fe74ff6185367a07aa
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As SGI-575 would need a dedicated scope for use, define the scope
'sgi575' under the subsection within Neoverse-RD platforms.
Change-Id: I872dc3bceace5c3358cde24fff1c4c17207ec962
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on A75/V1/N1 CPUs don't use SPMD_SPM_AT_SEL2, set its value to 0.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I59703ddd769f61778ea06cc183e1b163369281f1
Set build-option ENABLE_FEAT_AMU to 2 for RD-V1 and RD-V1-MC so that AMU
is enabled if the feature is implemented on these platforms. This would
ensure that lower ELs could access system registers relevant to AMU
without causing a trap to EL3.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I4d34db0c102c786f34103746064e22600d28da33
As the last step of refactoring the platform support of the first
generation of reference design platforms (A75/N1/V1), clean-up the
platform port definitions listed in the nrd_plat_arm_def1.h file.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I73a9b94f1db22192398ea8211109d2e4aaf965e1
As part of the refactoring for A75/V1/N1 CPU based platforms, remove
unused defines from the platform_def.h for each of these platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I37a6d82ad2f80a5c92b2652432fe2d211e052580
Presently, A75/V1/N1 CPU based platforms have platform port specific
macros defined within their platform_def.h file. To enhance organization
and appropriateness, relocate these definitions to
nrd_arm_platform_def1.h.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1f55192185df1509756bc2ef022e5aed0724dd05
The newly introduced nrd_ros_fw_def1.h file contains definitions that
have been refactored from other files. For better clarity, these
definitions are renamed appropriately with the prefix NRD_ROS to
denote that the definitions are for the rest of system (RoS) part
of the platform.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I4ecc76ca9250a68f7eca5d9a0d82c7674b34ca1d
The newly introduced nrd_ros_def1.h file contains definitions that
have been refactored from other files. For better clarity, these
definitions are renamed appropriately with the prefix NRD_ROS to
denote that the definitions are for the rest of system (RoS) part
of the platform. While at it, cleanup the platform ID related
definitions as well.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I12f559c82c62f05b9eed67baf9dd69d89f83a4da
The newly introduced nrd_css_fw_def1.h file contains definitions that
have been refactored from other files. For better clarity, these
definitions are renamed appropriately with the prefix NRD_CSS to denote
that the definitions are for the CSS.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8b9e52b4beb42aba1117df2db53daff96a7994bb
The newly introduced nrd_css_def1.h file contains definitions that have
been refactored from other files. For better clarity, these definitions
are renamed appropriately with the prefix NRD_CSS to denote that the
definitions are for the CSS.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie8bb32f96273cfa102a03fba3290b58051dac747
The CSS and RoS peripherals memory map macros have incorrect memory base
address and region size values. That is, the existing mmap definitions
are -
CSS peripherals mmap - Base address (0x20000000) and size (0x20000000)
RoS peripherals mmap - Base address (0x40000000) and size (0x40000000)
The corrected peripherals memory map definitions are -
CSS peripherals mmap - Base address (0x20000000) and size (0x40000000)
RoS peripherals mmap - Base address (0x60000000) and size (0x20000000)
While these macros are being updated, it is a good opportunity to rename
them appropriately. That is, the new macros are named as
NRD_CSS_PERIPH_MMAP - for mmap macro for CSS peripherals memory region
NRD_ROS_PERIPH_MMAP - for mmap macro for RoS peripherals memory region
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic2d12d7904922660a03efe6bc83ca8df2eb5a8d4
There are two macros that define ROS device memory map range and
attributes - one for local chip and the other for remote chip. Refactor
these two macros into a single macro that uses the chip ID to identify
the local or the remote chip.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iceb87f5fc319efa37105d66bb1c88b622a2bb366
