This node specifies the location of the MPAM registers for the DSU.
Rename the node to clarify this.
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ie870a7f31acbc44dd943e76896219b9bbdd7d5b4
remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.
Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC platforms, this patch appends the interrupt
properties in platform specific DT binding file.
Change-Id: I2ca505846f03ce64b8e5f02fd202962dbfe39f25
Signed-off-by: Leo Yan <leo.yan@arm.com>
The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.
Change-Id: Ia62a670e47cdc98b3c113a670a21edc65905cafe
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.
Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface.
Change-Id: Ic7a9d9ce927edbce02c7c09470a009dc56247240
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Define ppi-partitions for little, middle, and big cpu groups. PPI
affinity is expressed as a single "ppi-partitions" node, containing a
set of sub-nodes for each microarchitecture type, each with the
property 'affinity' which should be a list of phandles to CPU nodes.
PPI paritions are useful to affine specific PPI with set of CPUs
so that the drivers of micro-architecture specific nodes which uses
PPI can be divided based on CPU list e.g. SPE-PMU, CPU-PMU etc.
Change-Id: If7d47f71387ac982d2d992a0ce2de1652d564bd6
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is
a phandle to a node describing a set of CPUs this interrupt is affine
to.
If an interrupt is a PPI, and the node pointed in the 4th cell must be a
subnode of the "ppi-partitions" in the GIC node. For interrupt types
other than PPI, this cell must be zero. This is a preparison for
sequential changes for interrupt partitions, as the first step, it sets
all zeros for the interrupt affinity.
Change-Id: I66490a86a27aad5db6b1a42c2d8e0d042eee46a9
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
The usage for SMMU-700 is not consistent across TC platforms:
SMMU-700 on TC2:
| FVP | FPGA
--------+-------+------
Display | Used | Used
GPU | Used | Used
SMMU-700 on TC3:
| FVP | FPGA
--------+-------+------
Display | No | No
GPU | Used | No
This commit changes to use append mode for SMMU-700 to bind it on TC2
and TC3 separately. As a result, the TC_IOMMU_EN configuration is not
used, remove it.
Change-Id: Ic4152eb4c8ef97bf27b8a97c3c6cb86e32a2e8eb
Signed-off-by: Leo Yan <leo.yan@arm.com>
TC2 and TC3 have different the scmi shared memory regions and MHU
parameters, this patch appends the properties in scmi node for TC2 and
TC3 respectively.
Change-Id: Ifd001f780b575987877b4be36eb755a9dbe57e60
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
MHUv3's device tree is different from MHUv2's. Add support MHUv3 DT
binding for TC3 while keeping TC2 as-is.
Change-Id: Ib2f55d3a64a4cfe2ea9e62fe39d27ed54a2ca007
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
As only TC2 uses MHUv2, move the protocol property to tc2.dts.
Change-Id: I39dd57311e1058a6aabd4cbd5028511f704dd234
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
A Total Compute platform supports FVP and FPGA target. And it's possible
that these two targets have different hardware components. For this
reason, this patch introduces a new file tc-fpga.dtsi for FPGA related
DT binding.
As a result, this patch moves out FVP and FPGA specific macros into
tc-fvp.dtsi and tc-fpga.dtsi respectively.
Change-Id: I48d7d30d0c500cec5500f1a2a680e8b3a276ea99
Signed-off-by: Leo Yan <leo.yan@arm.com>
The main purpose of 'tc-base.dtsi' is for common DT bindings, however,
it contains bindings for platform specific.
This patch moves out these plaform specific bindings to 'tc2.dts' and
'tc3.dts' respectively.
Change-Id: I9355eeff539a3f2940190aef399b4fb4828cbbac
Signed-off-by: Leo Yan <leo.yan@arm.com>
Since now every TC board has its own dts file, this patch moves out the
platform specific code from tc_vers.dtsi to the corresponding platform
dts file.
Change-Id: I62e0872eddb2ae18e666a3f8dc0118a539651a9c
Signed-off-by: Leo Yan <leo.yan@arm.com>
Currently, the DT binding uses the file 'tc.dts' as a central place for
all TC platforms. And the variables (for different platforms, or FVP vs
FPGA, etc.) are maintained in 'tc_vers.dtsi'.
This patch renames 'tc.dts' to 'tc-base.dtsi' and creates an individual
.dts file for every platform. The purpose is to use 'tc-base.dtsi' for
maintaining common DT binding and every platform's specific definitions
will be moved into its own .dts file. This is a preparation for
sequential refactoring.
It changes to include the header files in platform DTS files but not in
the 'tc-base.dtsi'. This can allow 'tc-base.dtsi' is general enough and
platform DTS files covers platform specific defintions.
Change-Id: I034fb3f8836bcea36e8ad8ae01de41127693b0c6
Signed-off-by: Leo Yan <leo.yan@arm.com>
