mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
refactor(tc): move out platform specific DT binding from tc-base.dtsi
The main purpose of 'tc-base.dtsi' is for common DT bindings, however, it contains bindings for platform specific. This patch moves out these plaform specific bindings to 'tc2.dts' and 'tc3.dts' respectively. Change-Id: I9355eeff539a3f2940190aef399b4fb4828cbbac Signed-off-by: Leo Yan <leo.yan@arm.com>
This commit is contained in:
Leo Yan
parent
defcfb2b63
commit
f9565b2af1
3 changed files with 194 additions and 158 deletions
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@ -62,26 +62,6 @@
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core7 {
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cpu = <&CPU7>;
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};
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
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core8 {
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cpu = <&CPU8>;
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};
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core9 {
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cpu = <&CPU9>;
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};
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core10 {
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cpu = <&CPU10>;
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};
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core11 {
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cpu = <&CPU11>;
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};
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core12 {
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cpu = <&CPU12>;
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};
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core13 {
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cpu = <&CPU13>;
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};
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
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};
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};
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@ -162,13 +142,6 @@
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reg = <0x200>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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#if TARGET_PLATFORM <= 2
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clocks = <&scmi_dvfs 0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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#elif TARGET_PLATFORM == 3
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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#endif /* TARGET_PLATFORM == 3 */
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amu = <&amu>;
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supports-mpmm;
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};
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@ -179,13 +152,6 @@
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reg = <0x300>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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#if TARGET_PLATFORM <= 2
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clocks = <&scmi_dvfs 0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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#elif TARGET_PLATFORM == 3
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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#endif /* TARGET_PLATFORM == 3 */
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amu = <&amu>;
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supports-mpmm;
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};
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@ -220,13 +186,6 @@
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reg = <0x600>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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#if TARGET_PLATFORM <= 2
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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#elif TARGET_PLATFORM == 3
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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#endif /* TARGET_PLATFORM == 3 */
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amu = <&amu>;
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supports-mpmm;
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};
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@ -237,84 +196,9 @@
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reg = <0x700>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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#else
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
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amu = <&amu>;
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supports-mpmm;
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};
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
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CPU8:cpu@800 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x800>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU9:cpu@900 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x900>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU10:cpu@A00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xA00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU11:cpu@B00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xB00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU12:cpu@C00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xC00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 3>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU13:cpu@D00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xD00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 3>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
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};
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reserved-memory {
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@ -355,13 +239,6 @@
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cpu-pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
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<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
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,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
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<&CPU12>, <&CPU13>
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
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;
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};
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sram: sram@6000000 {
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@ -609,9 +486,6 @@
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#if TC_IOMMU_EN
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iommus = <&smmu_700 0x100>;
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#endif /* TC_IOMMU_EN */
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#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3)
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power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
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#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */
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pl0: pipeline@0 {
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reg = <0>;
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@ -692,38 +566,6 @@
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cpu = <&CPU7>;
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};
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
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ete8 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU8>;
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};
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ete9 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU9>;
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};
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ete10 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU10>;
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};
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ete11 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU11>;
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};
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ete12 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU12>;
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};
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ete13 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU13>;
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};
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
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trbe {
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compatible = "arm,trace-buffer-extension";
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interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>;
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165
fdts/tc2.dts
165
fdts/tc2.dts
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@ -36,9 +36,174 @@
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#include "tc-base.dtsi"
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/ {
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cpus {
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#if TARGET_FLAVOUR_FPGA
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cpu-map {
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cluster0 {
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core8 {
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cpu = <&CPU8>;
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};
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core9 {
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cpu = <&CPU9>;
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};
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core10 {
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cpu = <&CPU10>;
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};
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core11 {
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cpu = <&CPU11>;
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};
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core12 {
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cpu = <&CPU12>;
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};
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core13 {
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cpu = <&CPU13>;
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};
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};
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};
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#endif
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CPU2:cpu@200 {
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clocks = <&scmi_dvfs 0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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};
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CPU3:cpu@300 {
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clocks = <&scmi_dvfs 0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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};
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CPU6:cpu@600 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU7:cpu@700 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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#if TARGET_FLAVOUR_FPGA
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CPU8:cpu@800 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x800>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU9:cpu@900 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x900>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU10:cpu@A00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xA00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU11:cpu@B00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xB00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU12:cpu@C00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xC00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 3>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU13:cpu@D00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xD00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 3>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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#endif
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};
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#if TARGET_FLAVOUR_FPGA
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ete8 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU8>;
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};
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ete9 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU9>;
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};
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ete10 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU10>;
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};
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ete11 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU11>;
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};
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ete12 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU12>;
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};
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ete13 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU13>;
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};
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#endif /* TARGET_FLAVOUR_FPGA */
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cpu-pmu {
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#if TARGET_FLAVOUR_FPGA
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interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
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<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>,
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<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
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<&CPU12>, <&CPU13>;
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#else
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interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
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<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
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#endif
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};
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cmn-pmu {
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compatible = "arm,ci-700";
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reg = <0x0 0x50000000 0x0 0x10000000>;
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interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
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};
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dp0: display@DPU_ADDR {
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#if TC_SCMI_PD_CTRL_EN
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power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
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#endif
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};
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};
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29
fdts/tc3.dts
29
fdts/tc3.dts
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@ -33,3 +33,32 @@
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#include "tc-fvp.dtsi"
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#endif /* TARGET_FLAVOUR_FVP */
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#include "tc-base.dtsi"
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/ {
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cpus {
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CPU2:cpu@200 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU3:cpu@300 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU6:cpu@600 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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CPU7:cpu@700 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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};
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cpu-pmu {
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interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
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<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
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};
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};
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