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refactor(tc): move out platform specific code from tc_vers.dtsi

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Since now every TC board has its own dts file, this patch moves out the
platform specific code from tc_vers.dtsi to the corresponding platform
dts file.

Change-Id: I62e0872eddb2ae18e666a3f8dc0118a539651a9c
Signed-off-by: Leo Yan <leo.yan@arm.com>
This commit is contained in:
Leo Yan 2024-04-24 09:53:21 +01:00
parent b3a9737ce0
commit defcfb2b63
3 changed files with 46 additions and 48 deletions
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28
fdts/tc2.dts
View file

@ -9,8 +9,36 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>
#if TARGET_FLAVOUR_FVP
#define LIT_CAPACITY 406
#define MID_CAPACITY 912
#else /* TARGET_FLAVOUR_FPGA */
#define LIT_CAPACITY 280
#define MID_CAPACITY 775
/* this is an area optimized configuration of the big core */
#define BIG2_CAPACITY 930
#endif /* TARGET_FLAVOUR_FPGA */
#define BIG_CAPACITY 1024
#define INT_MBOX_RX 317
#define MHU_TX_ADDR 45000000 /* hex */
#define MHU_RX_ADDR 45010000 /* hex */
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ 5000000
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc-base.dtsi"
/ {
cmn-pmu {
compatible = "arm,ci-700";
reg = <0x0 0x50000000 0x0 0x10000000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
};
};

18
fdts/tc3.dts
View file

@ -10,6 +10,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>
#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024
#define INT_MBOX_RX 300
#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_RX_ADDR 46140000 /* hex */
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"

48
fdts/tc_vers.dtsi
View file

@ -13,37 +13,6 @@
#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2)
#endif /* TC_SCMI_PD_CTRL_EN */
/* All perf is normalized against the big core */
#define BIG_CAPACITY 1024
#if TARGET_PLATFORM <= 2
#if TARGET_FLAVOUR_FVP
#define LIT_CAPACITY 406
#define MID_CAPACITY 912
#else /* TARGET_FLAVOUR_FPGA */
#define LIT_CAPACITY 280
#define MID_CAPACITY 775
/* this is an area optimized configuration of the big core */
#define BIG2_CAPACITY 930
#endif /* TARGET_FLAVOUR_FPGA */
#define INT_MBOX_RX 317
#define MHU_TX_ADDR 45000000 /* hex */
#define MHU_RX_ADDR 45010000 /* hex */
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ 5000000
#elif TARGET_PLATFORM == 3
#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define INT_MBOX_RX 300
#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_RX_ADDR 46140000 /* hex */
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#endif /* TARGET_PLATFORM == 3 */
#if TARGET_FLAVOUR_FVP
#define STDOUT_PATH "serial0:115200n8"
#define GIC_CTRL_ADDR 2c010000
@ -62,13 +31,6 @@
vsync-len = <2>
#define ETH_COMPATIBLE "smsc,lan91c111"
#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0>
#if TARGET_PLATFORM <= 2
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#else /* TARGET_PLATFORM >= 3 */
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#endif /* TARGET_PLATFORM >= 3 */
#else /* TARGET_FLAVOUR_FPGA */
@ -90,8 +52,6 @@
vsync-len = <10>
#define ETH_COMPATIBLE "smsc,lan9115"
#define MMC_REMOVABLE non-removable
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif /* TARGET_FLAVOUR_FPGA */
/* Use SCMI controlled clocks */
@ -121,14 +81,6 @@
#endif /* !TC_DPU_USE_SCMI_CLK */
/ {
#if TARGET_PLATFORM <= 2
cmn-pmu {
compatible = "arm,ci-700";
reg = <0x0 0x50000000 0x0 0x10000000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
};
#endif /* TARGET_PLATFORM <= 2 */
#if !TC_DPU_USE_SCMI_CLK
dpu_aclk: dpu_aclk {
compatible = "fixed-clock";