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feat(tc): add PPI partitions in DT binding

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Define ppi-partitions for little, middle, and big cpu groups. PPI
affinity is expressed as a single "ppi-partitions" node, containing a
set of sub-nodes for each microarchitecture type, each with the
property 'affinity' which should be a list of phandles to CPU nodes.

PPI paritions are useful to affine specific PPI with set of CPUs
so that the drivers of micro-architecture specific nodes which uses
PPI can be divided based on CPU list e.g. SPE-PMU, CPU-PMU etc.

Change-Id: If7d47f71387ac982d2d992a0ce2de1652d564bd6
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
This commit is contained in:
Jagdish Gediya 2024-04-23 12:36:32 +01:00 • committed by Leo Yan
parent 1300bbce15
commit ebc991b3a1
2 changed files with 42 additions and 0 deletions
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26
fdts/tc2.dts
View file

@ -237,6 +237,32 @@
};
};
gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
};
#if TARGET_FLAVOUR_FVP
ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU4>, <&CPU5>, <&CPU6>;
};
ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU7>;
};
#elif TARGET_FLAVOUR_FPGA
ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, <&CPU8>;
};
ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU9>, <&CPU10>, <&CPU11>, <&CPU12>, <&CPU13>;
};
#endif
};
};
smmu_700: iommu@3f000000 {
status = "okay";
};

16
fdts/tc3.dts
View file

@ -116,6 +116,22 @@
};
};
gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
affinity = <&CPU0>, <&CPU1>;
};
ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};
ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU6>, <&CPU7>;
};
};
};
#if TARGET_FLAVOUR_FVP
smmu_700: iommu@3f000000 {
status = "okay";