* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct
feat(stm32mp1-fdts): remove RTC clock configuration
refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock
refactor(st-clock): driver size optimization
refactor(st-clock): remove BL32 support on STM32MP13
feat(st-clock): don't gate/ungate an oscillator if it is not wired
feat(dt-bindings): add missing SPIx bus clocks
feat(stm32mp1-fdts): remove PLL1 settings
feat(st-clock): update with new bindings
feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1
feat(dt-bindings): new RCC DT bindings
feat(stm32mp1): always boot at 650MHz
refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13
fix(st-clock): display proper PLL number for STM32MP13
fix(st-clock): do not reconfigure LSE
feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation
refactor(st-clock): remove unused clk function in API
refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config
feat(st-clock): add function to restore generic timer rate
RTC clock configuration is done now in OPTEE.
Note: The RTC clock source can only be configured once.
TF-A, configuring the RTC clock source will have no effect in OPTEE.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I111ba96b27d0de0c45086ba8ef947dd2e6785672
TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.
Change-Id: I0003337d8d37df7b2a70a84b5475f4278c4c4669
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
LSI was too slow to provide enough random numbers (limited
to 6ms for 16 bytes production). Switch to CSI that allow
to get the RNG fifo ready in less than 50µs.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I76d1fe58e2f4d5416a96f48123ae36bd82d8a8ee
Since the CoT device tree is intended solely for BL2, remove the
nodes that are not handled by BL2.
Change-Id: I977eec902f16de59743e97d15148d63934b7b863
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Add Dualroot CoT DTB, which allows Dualroot platforms to get their chain
of trust description from a configuration file, rather than hard-coding
it into the firmware source code itself.
Change-Id: I03af8f28ba7ad56b883ff5e7961500ffdb8c3957
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf driver can be used with perf.
Change-Id: I7e0ac5025231c3f19d5291292d4cae186accc544
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Add an `stdout-path' property into the `chosen' node of the Foundation
FVPs Devicetrees.
This gives a default console to the Linux kernel when "console=" is not
specified on the kernel command line, which is useful when booting with
U-Boot in UEFI for example.
Change-Id: I27d5f7f9416bd42b7401b1a57ae64bfee2524204
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
As per the GPU integration guide, adding the PBHA INT overrides to
influence the GPU allocation policy for the System Level Cache (SLC).
This commit uses SLC policy #23, which is the Arm SLC cache policy
number for GPUs. The cache policy #23 may not be optimal for all
workloads, although it outperforms other policies on the tested data
sets.
Change-Id: I19ddbcf52a2f01af0ab6dfd7cc25b2e438b9014a
Signed-off-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
The flag STM32MP15_OPTEE_RSV_SHM was disabled and mark deprecated.
Remove the corresponding code.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I948af3e1de4b89815c967a63abe64f285c405ecc
Enable full-HD resolution (1920x1080p60) for the FVP model, and add
checking for the passed resolution parameter.
Change-Id: I5e37ae79b5ceac088a18d5acf00ff4a557bb56aa
Signed-off-by: Sergio Alves <sergio.dasilvalves@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
TC2 and TC3 have different the scmi shared memory regions and MHU
parameters, this patch appends the properties in scmi node for TC2 and
TC3 respectively.
Change-Id: Ifd001f780b575987877b4be36eb755a9dbe57e60
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
MHUv3's device tree is different from MHUv2's. Add support MHUv3 DT
binding for TC3 while keeping TC2 as-is.
Change-Id: Ib2f55d3a64a4cfe2ea9e62fe39d27ed54a2ca007
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
As Linux 6.1 and later kernels require the SCMI nodes must be placed in
a firmware node, this patch adds the 'firmware' node and puts SCMI nodes
under it.
Change-Id: I37855095b8b0e5051c5de6e8db30e43f6220f9de
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
As only TC2 uses MHUv2, move the protocol property to tc2.dts.
Change-Id: I39dd57311e1058a6aabd4cbd5028511f704dd234
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
As the 'mhu-protocol' property is not used in mhu node, drop it.
Change-Id: I2f7320f668451ce44601dfa48bf47103334c39ed
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
This patch appends properties in DT bindings to differentiate between
FVP and FPGA. The related macros are no longer used, so they are
removed.
This patch contains minor improvement for adding labels in device nodes.
Change-Id: I8d708bb7a8a9a0ed32b806abcb4e7651daadf5e6
Signed-off-by: Leo Yan <leo.yan@arm.com>
As SCMI clock DT bindings are common for TC platforms, move them into
'tc-base.dtsi'.
As a result, the file 'tc_vers.dtsi' is empty, so removes it.
Change-Id: Iaa7219bbbde8458dcfe01de7ad6c277a960357c5
Signed-off-by: Leo Yan <leo.yan@arm.com>
A Total Compute platform supports FVP and FPGA target. And it's possible
that these two targets have different hardware components. For this
reason, this patch introduces a new file tc-fpga.dtsi for FPGA related
DT binding.
As a result, this patch moves out FVP and FPGA specific macros into
tc-fvp.dtsi and tc-fpga.dtsi respectively.
Change-Id: I48d7d30d0c500cec5500f1a2a680e8b3a276ea99
Signed-off-by: Leo Yan <leo.yan@arm.com>
The main purpose of 'tc-base.dtsi' is for common DT bindings, however,
it contains bindings for platform specific.
This patch moves out these plaform specific bindings to 'tc2.dts' and
'tc3.dts' respectively.
Change-Id: I9355eeff539a3f2940190aef399b4fb4828cbbac
Signed-off-by: Leo Yan <leo.yan@arm.com>
Since now every TC board has its own dts file, this patch moves out the
platform specific code from tc_vers.dtsi to the corresponding platform
dts file.
Change-Id: I62e0872eddb2ae18e666a3f8dc0118a539651a9c
Signed-off-by: Leo Yan <leo.yan@arm.com>
Currently, the DT binding uses the file 'tc.dts' as a central place for
all TC platforms. And the variables (for different platforms, or FVP vs
FPGA, etc.) are maintained in 'tc_vers.dtsi'.
This patch renames 'tc.dts' to 'tc-base.dtsi' and creates an individual
.dts file for every platform. The purpose is to use 'tc-base.dtsi' for
maintaining common DT binding and every platform's specific definitions
will be moved into its own .dts file. This is a preparation for
sequential refactoring.
It changes to include the header files in platform DTS files but not in
the 'tc-base.dtsi'. This can allow 'tc-base.dtsi' is general enough and
platform DTS files covers platform specific defintions.
Change-Id: I034fb3f8836bcea36e8ad8ae01de41127693b0c6
Signed-off-by: Leo Yan <leo.yan@arm.com>
To follow up the DT naming convention, this patch renames the file
'tc_fvp.dtsi' to 'tc-fvp.dtsi'.
Change-Id: Ib74cc38eb935d3daac87fbab6de4c004b1ceddcc
Signed-off-by: Leo Yan <leo.yan@arm.com>
Now some macros (e.g., MHU_RX_ADDR(0x), MHU_TX_ADDR(0x), etc) add the
prefix '0x' at the beginning of the addresses for hexadecimal values.
For better readability, this patch introduces a new macro ADDRESSIFY(),
which explictly adds the prefix '0x' for hexadecimal values. With this
new macro, address macros can drop the parameter and be simplified to
hexadecimal address value.
Change-Id: Idd1af0394f6ef8288fbff1fd4d86b1709d1c1d16
Signed-off-by: Leo Yan <leo.yan@arm.com>
Similarly to the memory node in the NS device tree, platform_def already
defines all the necessary values to populate the spmc manifest and NS
related entries automatically. Use the macros directly so any changes
can propagate automatically.
The result of this is that TC3 and above get correct secure world
manifests automatically. They were previously broken.
One "breaking" change is that the FWU region moves. This should have
happened previously but it was missed when the secure portion of DRAM
was increased, leaving it in secure memory. This was caught when going
over the definitions and correlating them should prevent this in the
future.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1415e402be8c70f5e22f28eabddcb53298c57a11
With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't come naturally. To avoid this, add the memory node such that it
uses the macros defined in platform_def.
By doing this we can put u-boot out of its misery in trying to come up
with the correct memory node and tf-a's device tree becomes complete.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia92cc6931abb12be2856ac3fb1455e4f3005b326
For u-boot to use the device tree itself it needs to know about the
arm_ffa module. This is not relevant to linux but it doesn't hurt as it
won't use it.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I6e75659e4950c62ce7377dc7941225eb5d7a3d8d
If the kernel is post 5.19 and is configured with
CONFIG_RANDOM_TRUST_BOOTLOADER=y then entropy can be passed to
Linux via the device tree. This avoids delaying the Linux boot
waiting for entropy. This is particularly noticeable when
booting android but also speeds up the generation of the ssl
certificates.
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Change-Id: I4c6136c54f0e971802a2a9de9f88cd32b610dce9
Currently there are two configurations for DPU
Config 1: Address - 0x2CC0_0000 IRQ - 101
Config 2: Address - 0x40_0000_0000 IRQ - 547
Config 1 is used by all FPGA and TC0, TC1 and TC2 FVPs
Config 2 is used by TC3 FVP currently
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: If0097441b6ab90f58911df032e45f6bf06fc7909
Compile-time controls have been added for the following:
* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU correctly
for DPU and GPU.
These will allow easier experimentation in the future without
ad-hoc changes needed in the dts file for any sort of analysis
that requires testing different paths.
For TC3 however, the DPU is in an always on power domain so SCMI power
domains are not supported.
Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1
In trying to use the same DTS for the FVP and FPGA subvariants we need
to keep track of what is different. Move the FVP RoS, which is different
to the FPGA's, to reduce the number of ifdefs and make FVP-only changes
easier.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib7999d3e39de55ab4a30e68dd81f95120be15a8c
Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The differences are:
* addresses of GIC and UART
* displays (FPGA uses 4k)
* ethernet devices and SD card (it's non removable on the FPGA)
Their frequencies are also different. The FVP simulates certain
frequencies but isn't very sensitive when we disregard them. To keep
code similar, update them with the FPGA values. This keeps working on
FVP even if slightly incorrect.
Also add an option for the DPU to either use fixed clocks or SCMI set
clocks, hidden behind a flag. This is useful during bringup and because
SCMI may not necessarily work on FPGA.
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Co-developed-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Co-developed-by: Usama Arif <usama.arif@arm.com>
Co-developed-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic7a4bfc302673a3a6571757e23a9e6184fba2a13
TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arrangement).
Introduce these differences and gate them behind a new TARGET_FLAVOUR
flag which defaults to FVP for compatibility.
While updating CPUs, it's a good time to do TC3 too. It has different
cores in a different configuration again, so it needs different capacity
values. Those have been derived using GeekBench 6.0 ST on the FPGA.
Finally GPU and DPU power domains are 1 above the CPUs so make that
relative.
In the end, the big/mid/little configurations are:
* TC2 FVP: 1/3/4
* TC2 FPGA: 2/3/5/4 (the 3 is a big "min" core)
* TC3 both: 2/4/2 (with new capacities)
Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3c3a10d6727f5010fd9026a404df27e9262dff6b
TC3 is a little different from TC2:
* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utility space address (needed for MPAM) is different
* no CMN (and therefore cmn-pmu)
* the uart clock is different
This requires the dts to be different between revisions for the first
time. Introduce a tc_vers.dtsi that includes only definitions for things
that are different.
Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2940d87a69ea93502b7f5a22a539e4b70a63e827
We have lots of errors in our device tree when running dt-validate.
Remove the majority so that dt-validate-ing is useful now.
Do this by renaming nodes to conform to spec, making addresses lowercase
with no 0x at the front, and removing nodes that shouldn't be there.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1840f0f5de34a56ee240c07eff08d73c856b338e
TC has PMUs with interrupts in all cores and Linux needs to be told
about them.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ice0e6dab396b90c05f4b9668623ba7b3556a53ac
The hdlcd device tree node is not in use for any TC incarnation. The DPU
replaces it. So drop it.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I5393435e36d8307bef909a6519cb40305b77f0cf
Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total compute platform. To make it fit with Op-tee we need to reduce
its available memory.
Also, reserve 4 MB for stmm communication used for firmware update.
The firmware update secure partition and u-boot communicates using the
stmm communication layer and it needs a dedicated memory region.
Co-developed-by: Sergio Alves <sergio.dasilvalves@arm.com>
Co-developed-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Tudor Cretu <tudor.cretu@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I0427549845f6c7650b8ef4e450d387fe9702a847
The gic and trbe0 are listed as active high, but the spec says they are
triggered on active low. Correct according to the spec.
While we're at it, convert all interrupts to use the macros so hopefully
no such confusion happens again.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2fc01cf0a34b031b95219b9656b613a19a2e9b2a
The scmi-perf-domain property is a custom property while we
wait for proper support in the kernel for using the scmi_pm_domain
driver and scmi_perf_domain driver at the same time.
GPU operating points are now in the SCP firmware.
Change-Id: Ib6d8f52c8bf69194b1d2da4e065a34c4a341c221
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Remap TF-A console logs from SoC UART2 (S1 terminal) to CSS
secure (UART1_AP terminal) and Linux logs from SoC UART2
(S1 terminal) to CSS non-secure (UART_AP terminal) to align
with the latest FVP TC2 model (version 11.23/17).
Change-Id: I7206e64b65346bfdcc48d6acd3792b436041e45f
Signed-off-by: Annam Sai Manisha <annam.saimanisha@arm.com>
