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Merge changes from topic "us_mcn" into integration

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* changes:
  feat(tc): configure MCN rdalloc and wralloc mode
  feat(tc): add dts entries for MCN PMU nodes
  feat(tc): enable MCN non-secure access to pmu counters on TC3
This commit is contained in:
Manish V Badarkhe 2024-06-14 12:18:50 +02:00 • committed by TrustedFirmware Code Review
commit 93ffd7c3dc
3 changed files with 93 additions and 0 deletions
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20
fdts/tc3.dts
View file

@ -72,6 +72,26 @@
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
};
cs-pmu@1 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
};
cs-pmu@2 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
};
cs-pmu@3 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
};
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";

33
plat/arm/board/tc/include/platform_def.h
View file

@ -413,4 +413,37 @@
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK
#define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK
#if TARGET_PLATFORM == 3
#define NCI_BASE_ADDR UL(0x4F000000)
#ifdef TARGET_FLAVOUR_FPGA
#define MCN_ADDRESS_SPACE_SIZE 0x00120000
#else
#define MCN_ADDRESS_SPACE_SIZE 0x00130000
#endif /* TARGET_FLAVOUR_FPGA */
#define MCN_OFFSET_IN_NCI 0x00C90000
#define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI)
#define MCN_PMU_OFFSET 0x000C4000
#define MCN_MICROARCH_OFFSET 0x000E4000
#define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET)
#define MCN_SCR_OFFSET 0x4
#define MCN_SCR_PMU_BIT 10
#define MCN_INSTANCES 4
#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \
(n * MCN_ADDRESS_SPACE_SIZE) + \
MCN_PMU_OFFSET)
#define MCN_MPAM_NS_OFFSET 0x000D0000
#define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET)
#define MCN_MPAM_S_OFFSET 0x000D4000
#define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET)
#define MPAM_SLCCFG_CTL_OFFSET 0x00003018
#define SLC_RDALLOCMODE_SHIFT 8
#define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT)
#define SLC_WRALLOCMODE_SHIFT 12
#define SLC_WRALLOCMODE_MASK (3 << SLC_WRALLOCMODE_SHIFT)
#define SLC_DONT_ALLOC 0
#define SLC_ALWAYS_ALLOC 1
#define SLC_ALLOC_BUS_SIGNAL_ATTR 2
#endif /* TARGET_PLATFORM == 3 */
#endif /* PLATFORM_DEF_H */

40
plat/arm/board/tc/tc_bl31_setup.c
View file

@ -66,11 +66,51 @@ static scmi_channel_plat_info_t tc_scmi_plat_info = {
.db_modify_mask = 0x1,
.ring_doorbell = &mhu_ring_doorbell,
};
static void enable_ns_mcn_pmu(void)
{
/*
* Enable non-secure access to MCN PMU registers
*/
for (int i = 0; i < MCN_INSTANCES; i++) {
uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR + MCN_SCR_OFFSET +
(i * MCN_ADDRESS_SPACE_SIZE);
mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT);
}
}
static void set_mcn_slc_alloc_mode(void)
{
/*
* SLC WRALLOCMODE and RDALLOCMODE are configured by default to
* 0b01 (always alloc), configure both to 0b10 (use bus signal
* attribute from interface).
*/
for (int i = 0; i < MCN_INSTANCES; i++) {
uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR +
(i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR +
(i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
mmio_clrsetbits_32(slccfg_ctl_ns,
(SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
(SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
(SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
mmio_clrsetbits_32(slccfg_ctl_s,
(SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
(SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
(SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
}
}
#endif
void bl31_platform_setup(void)
{
tc_bl31_common_platform_setup();
#if TARGET_PLATFORM == 3
enable_ns_mcn_pmu();
set_mcn_slc_alloc_mode();
#endif
}
scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused)